Digital Filters

The new technology advances provide that a great number of system signals can be easily measured with a low cost. The main problem is that usually only a fraction of the signal is useful for different purposes, for example maintenance, DVD-recorders, computers, electric/electronic circuits, econometric, optimization, etc. Digital filters are the most versatile, practical and effective methods for extracting the information necessary from the signal. They can be dynamic, so they can be automatically or manually adjusted to the external and internal conditions. Presented in this book are the most advanced digital filters including different case studies and the most relevant literature

Multiplierless CSD techniques for high performance FPGA implementation of digital filters.

I leverage FastCSD to develop a new, high performance iterative multiplierless structure based on a novel real-time CSD recoding, so that more zero partial products are introduced. Up to 66.7% zero partial products occur compared to 50% in the traditional modified Booth's recoding. Also, this structure reduces the non-zero partial products to a minimum. As a result, the number of arithmetic operations in the carry-save structure is reduced. Thus, an overall speed-up, as well as low-power consumption can be achieved. Furthermore, because the proposed structure involves real time CSD recoding and does not require a fixed value for the multiplier input to be known a priori, the proposed multiplier can be applied to implement digital filters with non-fixed filter coefficients, such as adaptive filters.My work is based on a dramatic new technique for converting between 2's complement and CSD number systems, and results in high-performance structures that are particularly effective for implementing adaptive systems in reconfigurable logic.My research focus is on two key ideas for improving DSP performance: (1) Develop new high performance, efficient shift-add techniques ("multiplierless") to implement the multiply-add operations without the need for a traditional multiplier structure. (2) There is a growing trend toward design prototyping and even production in FPGAs as opposed to dedicated DSP processors or ASICs; leverage this trend synergistically with the new multiplierless structures to improve performance.Implementation of digital signal processing (DSP) algorithms in hardware, such as field programmable gate arrays (FPGAs), requires a large number of multipliers. Fast, low area multiply-adds have become critical in modern commercial and military DSP applications. In many contemporary real-time DSP and multimedia applications, system performance is severely impacted by the limitations of currently available speed, energy efficiency, and area requirement of an onboard silicon multiplier.I also introduce a new multi-input Canonical Signed Digit (CSD) multiplier unit, which requires fewer shift/add/subtract operations and reduced CSD number conversion overhead compared to existing techniques. This results in reduced power consumption and area requirements in the hardware implementation of DSP algorithms. Furthermore, because all the products are produced simultaneously, the multiplication speed and thus the throughput are improved. The multi-input multiplier unit is applied to implement digital filters with non-fixed filter coefficients, such as adaptive filters. The implementation cost of these digital filters can be further reduced by limiting the wordlength of the input signal with little or no sacrifice to the filter performance, which is confirmed by my simulation results. The proposed multiplier unit can also be applied to other DSP algorithms, such as digital filter banks or matrix and vector multiplications.Finally, the tradeoff between filter order and coefficient length in the design and implementation of high-performance filters in Field Programmable Gate Arrays (FPGAs) is discussed. Non-minimum order FIR filters are designed for implementation using Canonical Signed Digit (CSD) multiplierless implementation techniques. By increasing the filter order, the length of the coefficients can be decreased without reducing the filter performance. Thus, an overall hardware savings can be achieved.Adaptive system implementations require real-time conversion of coefficients to Canonical Signed Digit (CSD) or similar representations to benefit from multiplierless techniques for implementing filters. Multiplierless approaches are used to reduce the hardware and increase the throughput. This dissertation introduces the first non-iterative hardware algorithm to convert 2's complement numbers to their CSD representations (FastCSD) using a fixed number of shift and logic operations. As a result, the power consumption and area requirements required for hardware implementation of DSP algorithms in which the coefficients are not known a priori can be greatly reduced. Because all CSD digits are produced simultaneously, the conversion speed and thus the throughput are improved when compared to overlap-and-scan techniques such as Booth's recoding

New design method of FIR filters with SP2 coefficients based on a new linear programming relaxation with triangle inequalities

Publication in the conference proceedings of EUSIPCO, Toulouse, France, 200

Passive cascaded-lattice structures for low-sensitivity FIR filter design, with applications to filter banks

A class of nonrecursive cascaded-lattice structures is derived, for the implementation of finite-impulse response (FIR) digital filters. The building blocks are lossless and the transfer function can be implemented as a sequence of planar rotations. The structures can be used for the synthesis of any scalar FIR transfer function H(z) with no restriction on the location of zeros; at the same time, all the lattice coefficients have magnitude bounded above by unity. The structures have excellent passband sensitivity because of inherent passivity, and are automatically internally scaled, in an L_2 sense. The ideas are also extended for the realization of a bank of MFIR transfer functions as a cascaded lattice. Applications of these structures in subband coding and in multirate signal processing are outlined. Numerical design examples are included

Algorithms and Circuits for Analog-Digital Hybrid Multibeam Arrays

Fifth generation (5G) and beyond wireless communication systems will rely heavily on larger antenna arrays combined with beamforming to mitigate the high free-space path-loss that prevails in millimeter-wave (mmW) and above frequencies. Sharp beams that can support wide bandwidths are desired both at the transmitter and the receiver to leverage the glut of bandwidth available at these frequency bands. Further, multiple simultaneous sharp beams are imperative for such systems to exploit mmW/sub-THz wireless channels using multiple reflected paths simultaneously. Therefore, multibeam antenna arrays that can support wider bandwidths are a key enabler for 5G and beyond systems. In general, N-beam systems using N-element antenna arrays will involve circuit complexities of the order of N2. This dissertation investigates new analog, digital and hybrid low complexity multibeam beamforming algorithms and circuits for reducing the associated high size, weight, and power (SWaP) complexities in larger multibeam arrays. The research efforts on the digital beamforming aspect propose the use of a new class of discrete Fourier transform (DFT) approximations for multibeam generation to eliminate the need for digital multipliers in the beamforming circuitry. For this, 8-, 16- and 32-beam multiplierless multibeam algorithms have been proposed for uniform linear array applications. A 2.4 GHz 16-element array receiver setup and a 5.8 GHz 32-element array receiver system which use field programmable gate arrays (FPGAs) as digital backend have been built for real-time experimental verification of the digital multiplierless algorithms. The multiplierless algorithms have been experimentally verified by digitally measuring beams. It has been shown that the measured beams from the multiplierless algorithms are in good agreement with the exact counterpart algorithms. Analog realizations of the proposed approximate DFT transforms have also been investigated leading to low-complex, high bandwidth circuits in CMOS. Further, a novel approach for reducing the circuit complexity of analog true-time delay (TTD) N-beam beamforming networks using N-element arrays has been proposed for wideband squint-free operation. A sparse factorization of the N-beam delay Vandermonde beamforming matrix is used to reduce the total amount of TTD elements that are needed for obtaining N number of beams in a wideband array. The method has been verified using measured responses of CMOS all-pass filters (APFs). The wideband squint-free multibeam algorithm is also used to propose a new low-complexity hybrid beamforming architecture targeting future 5G mmW systems. Apart from that, the dissertation also explores multibeam beamforming architectures for uniform circular arrays (UCAs). An algorithm having N log N circuit complexity for simultaneous generation of N-beams in an N-element UCA is explored and verified

Wavelets and multirate filter banks : theory, structure, design, and applications

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Civil and Environmental Engineering, 2004.Includes bibliographical references (p. 219-230) and index.Wavelets and filter banks have revolutionized signal processing with their ability to process data at multiple temporal and spatial resolutions. Fundamentally, continuous-time wavelets are governed by discrete-time filter banks with properties such as perfect reconstruction, linear phase and regularity. In this thesis, we study multi-channel filter bank factorization and parameterization strategies, which facilitate designs with specified properties that are enforced by the actual factorization structure. For M-channel filter banks (M =/> 2), we develop a complete factorization, M-channel lifting factorization, using simple ladder-like structures as predictions between channels to provide robust and efficient implementation; perfect reconstruction is structurally enforced, even under finite precision arithmetic and quantization of lifting coefficients. With lifting, optimal low-complexity integer wavelet transforms can thus be designed using a simple and fast algorithm that incorporates prescribed limits on hardware operations for power-constrained environments. As filter bank regularity is important for a variety of reasons, an aspect of particular interest is the structural imposition of regularity onto factorizations based on the dyadic form uvt. We derive the corresponding structural conditions for regularity, for which M-channel lifting factorization provides an essential parameterization. As a result, we are able to design filter banks that are exactly regular and amenable to fast implementations with perfect reconstruction, regardless of the choice of free parameters and possible finite precision effects. Further constraining u = v ensures regular orthogonal filter banks,(cont.) whereas a special dyadic form is developed that guarantees linear phase. We achieve superior coding gains within 0.1% of the optimum, and benchmarks conducted on image compression applications show clear improvements in perceptual and objective performance. We also consider the problem of completing an M-channel filter bank, given only its scaling filter. M-channel lifting factorization can efficiently complete such biorthogonal filter banks. On the other hand, an improved scheme for completing paraunitary filter banks is made possible by a novel order-one factorization which allows greater design flexibility, resulting in improved frequency selectivity and energy compaction over existing state of the art methods. In a dual setting, the technique can be applied to transmultiplexer design to achieve higher-rate data transmissions.by Ying-Jui Chen.Ph.D

Multiplierless multirate FIR filter design and implementation

Ph.DDOCTOR OF PHILOSOPH

A Lattice Basis Reduction Approach for the Design of Finite Wordlength FIR Filters

International audienceMany applications of finite impulse response (FIR) digital filters impose strict format constraints for the filter coefficients. Such requirements increase the complexity of determining optimal designs for the problem at hand. We introduce a fast and efficient method, based on the computation of good nodes for polynomial interpolation and Euclidean lattice basis reduction. Experiments show that it returns quasi-optimal finite wordlength FIR filters; compared to previous approaches it also scales remarkably well (length 125 filters are treated in < 9s). It also proves useful for accelerating the determination of optimal finite wordlength FIR filters