2,715 research outputs found

    An Accurate Timing Model for Fault Simulation in MOS Circuits

    Get PDF
    Coordinated Science Laboratory was formerly known as Control Systems LaboratorySemiconductor Research Corporation / 88-DP-109Joint Services Electronics Program / N00014-84-C-0149U of I OnlyRestricted to UIUC communit

    The Rolf of Test Chips in Coordinating Logic and Circuit Design and Layout Aids for VLSI

    Get PDF
    This paper emphasizes the need for multipurpose test chips and comprehensive procedures for use in supplying accurate input data to both logic and circuit simulators and chip layout aids. It is shown that the location of test structures within test chips is critical in obtaining representative data, because geometrical distortions introduced during the photomasking process can lead to significant intrachip parameter variations. In order to transfer test chip designs quickly, accurately, and economically, a commonly accepted portable chip layout notation and commonly accepted parametric tester language are needed. In order to measure test chips more accurately and more rapidly, parametric testers with improved architecture need to be developed in conjunction with innovative test structures with on-chip signal conditioning

    Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

    Get PDF
    Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis

    Product assurance technology for custom LSI/VLSI electronics

    Get PDF
    The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

    Study of switching transients in high frequency converters

    Get PDF
    As the semiconductor technologies progress rapidly, the power densities and switching frequencies of many power devices are improved. With the existing technology, high frequency power systems become possible. Use of such a system is advantageous in many aspects. A high frequency ac source is used as the direct input to an ac/ac pulse-density-modulation (PDM) converter. This converter is a new concept which employs zero voltage switching techniques. However, the development of this converter is still in its infancy stage. There are problems associated with this converter such as a high on-voltage drop, switching transients, and zero-crossing detecting. Considering these problems, the switching speed and power handling capabilities of the MOS-Controlled Thyristor (MCT) makes the device the most promising candidate for this application. A complete insight of component considerations for building an ac/ac PDM converter for a high frequency power system is addressed. A power device review is first presented. The ac/ac PDM converter requires switches that can conduct bi-directional current and block bi-directional voltage. These bi-directional switches can be constructed using existing power devices. Different bi-directional switches for the converter are investigated. Detailed experimental studies of the characteristics of the MCT under hard switching and zero-voltage switching are also presented. One disadvantage of an ac/ac converter is that turn-on and turn-off of the switches has to be completed instantaneously when the ac source is at zero voltage. Otherwise shoot-through current or voltage spikes can occur which can be hazardous to the devices. In order for the devices to switch softly in the safe operating area even under non-ideal cases, a unique snubber circuit is used in each bi-directional switch. Detailed theory and experimental results for circuits using these snubbers are presented. A current regulated ac/ac PDM converter built using MCT's and IGBT's is evaluated

    Statistical circuit simulations - from ‘atomistic’ compact models to statistical standard cell characterisation

    Get PDF
    This thesis describes the development and application of statistical circuit simulation methodologies to analyse digital circuits subject to intrinsic parameter fluctuations. The specific nature of intrinsic parameter fluctuations are discussed, and we explain the crucial importance to the semiconductor industry of developing design tools which accurately account for their effects. Current work in the area is reviewed, and three important factors are made clear: any statistical circuit simulation methodology must be based on physically correct, predictive models of device variability; the statistical compact models describing device operation must be characterised for accurate transient analysis of circuits; analysis must be carried out on realistic circuit components. Improving on previous efforts in the field, we posit a statistical circuit simulation methodology which accounts for all three of these factors. The established 3-D Glasgow atomistic simulator is employed to predict electrical characteristics for devices aimed at digital circuit applications, with gate lengths from 35 nm to 13 nm. Using these electrical characteristics, extraction of BSIM4 compact models is carried out and their accuracy in performing transient analysis using SPICE is validated against well characterised mixed-mode TCAD simulation results for 35 nm devices. Static d.c. simulations are performed to test the methodology, and a useful analytic model to predict hard logic fault limitations on CMOS supply voltage scaling is derived as part of this work. Using our toolset, the effect of statistical variability introduced by random discrete dopants on the dynamic behaviour of inverters is studied in detail. As devices scaled, dynamic noise margin variation of an inverter is increased and higher output load or input slew rate improves the noise margins and its variation. Intrinsic delay variation based on CV/I delay metric is also compared using ION and IEFF definitions where the best estimate is obtained when considering ION and input transition time variations. Critical delay distribution of a path is also investigated where it is shown non-Gaussian. Finally, the impact of the cell input slew rate definition on the accuracy of the inverter cell timing characterisation in NLDM format is investigated

    Effect of wearout processes on the critical timing parameters and reliability of CMOS bistable circuits

    Get PDF
    The objective of the research presented in this thesis was to investigate the effects of wearout processes on the performance and reliability of CMOS bistable circuits. The main wearout process affecting reliability of submicron MOS devices was identified as hot-carrier stress (and the resulting degradation in circuit performance). The effect of hot-carrier degradation on the resolving time leading to metastability of the bistable circuits also have been investigated. Hot-carrier degradation was identified as a major reliability concern for CMOS bistable circuits designed using submicron technologies. The major hot-carrier effects are the impact ionisation of hot- carriers in the channel of a MOS device and the resulting substrate current and gate current generation. The substrate current has been used as the monitor for the hot-carrier stress and have developed a substrate current model based on existing models that have been extended to incorporate additional effects for submicron devices. The optimisation of the substrate current model led to the development of degradation and life-time models. These are presented in the thesis. A number of bistable circuits designed using 0.7 micron CMOS technology design rules were selected for the substrate current model analysis. The circuits were simulated using a set of optimised SPICE model parameters and the stress factors on each device was evaluated using the substrate current model implemented as a post processor to the SPICE simulation. Model parameters for each device in the bistable were degraded according to the stress experienced and simulated again to determine the degradation in characteristic timing parameters for a predetermined stress period. A comparative study of the effect of degradation on characteristic timing parameters for a number of latch circuits was carried out. The life-times of the bistables were determined using the life-time model. The bistable circuits were found to enter a metastable state under critical timing conditions. The effect of hot-carrier stress induced degradation on the metastable state operation of the bistables were analysed. Based on the analysis of the hot-carrier degradation effects on the latch circuits, techniques are suggested to reduce hot-carrier stress and to improve circuit life-time. Modifications for improving hot- carrier reliability were incorporated into all the bistable circuits which were re-simulated to determine the improvement in life-time and reliability of the circuits under hot-carrier stress. The improved circuits were degraded based on the new stress factors and the degradation effects on the critical timing parameters evaluated and these were compared with those before the modifications. The improvements in the life-time and the reliability of the selected bistable circuits were quantified. It has been demonstrated that the hot-carrier reliability for all the selected bistable circuits can be improved by design techniques to reduce the stress on identified critically stressed devices
    • …
    corecore