Capacitance-to-Digital Converter for Harvested Systems Down to 0.3 V With No Trimming, Reference, and Voltage Regulation

In this work, a capacitance-to-digital converter (CDC) suitable for direct energy harvesting is introduced. The nW peak power and the ability to operate at any supply voltage in the 0.3-1.8 V range allow complete suppression of any intermediate DC-DC conversion, and hence direct supply provision from the harvester, as demonstrated with a mm-scale solar cell. The proposed CDC architecture eliminates the need for any additional support circuitry, preserving true nW-power operation, and reducing design and integration effort. In detail, the architecture is based on a pair of double-swappable oscillators, and avoids the need for any voltage/current/frequency reference circuit in the oscillator mismatch compensation. The digital and differential nature of the architecture counteracts the effect of process/voltage/temperature variations. A load-agnostic one-time self-calibration scheme compensates mismatch, and can be run from boot to run stage of the chip lifecycle. The proposed self-calibration scheme suppresses any trimming or testing time for low-cost systems, and avoids any input capacitance disconnection requirement. A 180-nm testchip shows 7-bit ENOB down to 0.3 V and 1.37-nW total power, when powered by a 1-mm2 indoor solar cell down to 10 lux (i.e., late twilight

Contribution to time domain readout circuits design for multi-standard sensing system for low voltage supply and high-resolution applications

Mención Internacional en el título de doctorThis research activity has the purpose of open new possibilities in the design of capacitance-to-digital converters (CDCs) by developing a solution based on time domain conversion. This can be applied to applications related with the Internet-of-Things (IoT). These applications are present in any electronic devices where sensing is needed. To be able to reduce the area of the whole system with the required performance, micro-electromechanical systems (MEMS) sensors are used in these applications. We propose a new family of sensor readout electronics to be integrated with MEMS sensors. Within the time domain converters, Dual Slope (DS) topology is very interesting to explore a new compromise between performances, area and power consumption. DS topology has been extensively used in instrumentation. The simplicity and robustness of the blocks inside classical DS converters it is the main advantage. However, they are not efficient for applications where higher bandwidth is required. To extend the bandwidth, DS converters have been introduced into ΔΣ loops. This topology has been named as integrating converters. They increase the bandwidth compare to classical DS architecture but at the expense of higher complexity. In this work we propose the use of a new family of DS converters that keep the advantages of the classical architecture and introduce noise shaping. This way the bandwidth is increased without extra blocks. The Self-Compensated noise-shaped DS converter (the name given to the new topology) keeps the signal transfer function (STF) and the noise transfer function (NTF) of Integrating converters. However, we introduce a new arrangement in the core of the converter to do noise shaping without extra circuitry. This way the simplicity of the architecture is preserved. We propose to use the Self-Compensated DS converter as a CDC for MEMS sensors. This work makes a study of the best possible integration of the two blocks to keep the signal integrity considering the electromechanical behavior of the sensor. The purpose of this front-end is to be connected to any kind of capacitive MEMS sensor. However, to prove the concepts developed in this thesis the architecture has been connected to a pressure MEMS sensor. An experimental prototype was implemented in 130-nm CMOS process using the architecture mentioned before. A peak SNR of 103.9 dB (equivalent to 1Pa) has been achieved within a time measurement of 20 ms. The final prototype has a power consumption of 220 μW with an effective area of 0.317 mm2. The designed architecture shows good performance having competitive numbers against high resolution topologies in amplitude domain.Esta actividad de investigación tiene el propósito de explorar nuevas posibilidades en el diseño de convertidores de capacitancia a digital (CDC) mediante el desarrollo de una solución basada en la conversión en el dominio del tiempo. Estos convertidores se pueden utilizar en aplicaciones relacionadas con el mercado del Internet-de-las-cosas (IoT). Hoy en día, estas aplicaciones están presentes en cualquier dispositivo electrónico donde se necesite sensar una magnitud. Para poder reducir el área de todo el sistema con el rendimiento requerido, se utilizan sensores de sistemas micro-electromecánicos (MEMS) en estas aplicaciones. Proponemos una nueva familia de electrónica de acondicionamiento para integrar con sensores MEMS. Dentro de los convertidores de dominio de tiempo, la topología del doble-rampa (DS) es muy interesante para explorar un nuevo compromiso entre rendimiento, área y consumo de energía. La topología de DS se ha usado ampliamente en instrumentación. La simplicidad y la solidez de los bloques dentro de los convertidores DS clásicos es la principal ventaja. Sin embargo, no son eficientes para aplicaciones donde se requiere mayor ancho de banda. Para ampliar el ancho de banda, los convertidores DS se han introducido en bucles ΔΣ. Esta topología ha sido nombrada como Integrating converters. Esta topología aumenta el ancho de banda en comparación con la arquitectura clásica de DS, pero a expensas de una mayor complejidad. En este trabajo, proponemos el uso de una nueva familia de convertidores DS que mantienen las ventajas de la arquitectura clásica e introducen la configuración del ruido. De esta forma, el ancho de banda aumenta sin bloques adicionales. El convertidor Self-Compensated noise-shaped DS (el nombre dado a la nueva topología) mantiene la función de transferencia de señal (STF) y la función de transferencia de ruido (NTF) de los Integrating converters. Sin embargo, presentamos una nueva topología en el núcleo del convertidor para conformar el ruido sin circuitos adicionales. De esta manera, se preserva la simplicidad de la arquitectura. Proponemos utilizar el Self-Compensated noise-shaped DS como un CDC para sensores MEMS. Este trabajo hace un estudio de la mejor integración posible de los dos bloques para mantener la integridad de la señal considerando el comportamiento electromecánico del sensor. El propósito de este circuito de acondicionamiento es conectarse a cualquier tipo de sensor MEMS capacitivo. Sin embargo, para demostrar los conceptos desarrollados en esta tesis, la arquitectura se ha conectado a un sensor MEMS de presión. Se ha implementado dos prototipos experimentales en un proceso CMOS de 130-nm utilizando la arquitectura mencionada anteriormente. Se ha logrado una relación señal-ruido máxima de 103.9 dB (equivalente a 1 Pa) con un tiempo de medida de 20 ms. El prototipo final tiene un consumo de energía de 220 μW con un área efectiva de 0.317 mm2. La arquitectura diseñada muestra un buen rendimiento comparable con las arquitecturas en el dominio de la amplitud que muestran resoluciones equivalentes.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Pieter Rombouts.- Secretario: Alberto Rodríguez Pérez.- Vocal: Dietmar Strãußnig

Design and Control of Power Converters for High Power-Quality Interface with Utility and Aviation Grids

Power electronics as a subject integrating power devices, electric and electronic circuits, control, and thermal and mechanic design, requires not only knowledge and engineering insight for each subarea, but also understanding of interface issues when incorporating these different areas into high performance converter design.Addressing these fundamental questions, the dissertation studies design and control issues in three types of power converters applied in low-frequency high-power transmission, medium-frequency converter emulated grid, and high-frequency high-density aviation grid, respectively, with the focus on discovering, understanding, and mitigating interface issues to improve power quality and converter performance, and to reduce the noise emission.For hybrid ac/dc power transmission,• Analyze the interface transformer saturation issue between ac and dc power flow under line unbalances.• Proposed both passive transformer design and active hybrid-line-impedance-conditioner to suppress this issue.For transmission line emulator,• Propose general transmission line emulation schemes with extension capability.• Analyze and actively suppress the effects of sensing/sampling bias and PWM ripple on emulation considering interfaced grid impedance.• Analyze the stability issue caused by interaction of the emulator and its interfaced impedance. A criterion that determines the stability and impedance boundary of the emulator is proposed.For aircraft battery charger,• Investigate architectures for dual-input and dual-output battery charger, and a three-level integrated topology using GaN devices is proposed to achieve high density.• Identify and analyze the mechanisms and impacts of high switching frequency, di/dt, dv/dt on sensing and power quality control; mitigate solutions are proposed.• Model and compensate the distortion due to charging transition of device junction capacitances in three-level converters.• Find the previously overlooked device junction capacitance of the nonactive devices in three-level converters, and analyze the impacts on switching loss, device stress, and current distortion. A loss calculation method is proposed using the data from the conventional double pulse tester.• Establish fundamental knowledge on performance degradation of EMI filters. The impacts and mechanisms of both inductive and capacitive coupling on different filter structures are understood. Characterization methodology including measuring, modeling, and prediction of filter insertion loss is proposed. Mitigation solutions are proposed to reduce inter-component coupling and self-parasitics

Interface Circuits for Microsensor Integrated Systems

ca. 200 words; this text will present the book in all promotional forms (e.g. flyers). Please describe the book in straightforward and consumer-friendly terms. [Recent advances in sensing technologies, especially those for Microsensor Integrated Systems, have led to several new commercial applications. Among these, low voltage and low power circuit architectures have gained growing attention, being suitable for portable long battery life devices. The aim is to improve the performances of actual interface circuits and systems, both in terms of voltage mode and current mode, in order to overcome the potential problems due to technology scaling and different technology integrations. Related problems, especially those concerning parasitics, lead to a severe interface design attention, especially concerning the analog front-end and novel and smart architecture must be explored and tested, both at simulation and prototype level. Moreover, the growing demand for autonomous systems gets even harder the interface design due to the need of energy-aware cost-effective circuit interfaces integrating, where possible, energy harvesting solutions. The objective of this Special Issue is to explore the potential solutions to overcome actual limitations in sensor interface circuits and systems, especially those for low voltage and low power Microsensor Integrated Systems. The present Special Issue aims to present and highlight the advances and the latest novel and emergent results on this topic, showing best practices, implementations and applications. The Guest Editors invite to submit original research contributions dealing with sensor interfacing related to this specific topic. Additionally, application oriented and review papers are encouraged.

A Study on Energy-Efficient Inductor Current Controls for Maximum Energy Delivery in Battery-free Buck Converter

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2017. 2. 김재하.A discontinuous conduction mode (DCM) buck converter, which acts as a voltage regulator in battery-free applications, is proposed to maximize the ener-gy delivery to the load system. In this work, we focus the energy loss problem during start-up and steady-state operation of the buck converter, which severely limits the energy delivery. Especially, the energy loss problem arises from the fact that there is no constant power source such as a battery and the only a small amount of energy harvested from the ambient energy sources is available. To address such energy loss problem, this dissertation proposes optimal induc-tor current control techniques at each operation to greatly reduce the energy losses. First, a switching-based stepwise capacitor charging scheme is presented that can charge the output capacitor with constant inductor current during start-up operation. By switching the inductor with gradually incrementing duty-cycle ratios in a stepwise fashion, the buck converter can make the inductor current a constant current source, which can greatly reduce the start-up energy loss com-pared to that in the conventional capacitor charging scheme with a voltage source. Second, a variable on-time (VOT) pulse-frequency-modulation (PFM) scheme is presented that can keep the peak inductor current constant during steady-state operation. By adaptively varying the on-time according to the op-erating voltage conditions of the buck converter, it can suppress the voltage ripple and improve the power efficiency even with a small output capacitor. Third, an adaptive off-time positioning zero-crossing detector (AOP-ZCD) is presented that can adaptively position the turn-off timing of the low-side switch close to the zero-inductor-current timing by predicting the inductor current waveform without using a power-hungry continuous-time ZCD. To demonstrate the proposed design concepts, the prototype battery-free wireless remote switch including the piezoelectric energy harvester and the proposed buck converter was fabricated in a 250 nm high-voltage CMOS technology. It can harvest a total energy of 246 μJ from a single button press action of a 300-mm2 lead magnesium niobate-lead titanate (PMN-PT) piezoelectric disc, and deliver more than 200 μJ to the load, which is sufficient to transmit a 4-byte-long message via 2.4-GHz wireless USB channel over a 10-m distance. If such battery-free application does not use the proposed buck converter, the energy losses in-curred at the buck converter would be larger than the energy harvested, and therefore it cannot operate with a single button-pressing action. Furthermore, thanks to the proposed energy efficient buck converter, the battery-free wire-less remote switch can be realized by using a cheaper PZT piezoelectric source, which can achieve a 10× cost reduction.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS CONTRIBUTION AND ORGANIZATION 6 CHAPTER 2 OPERATION MODE AND OVERALL ARCHITECTURE 8 2.1 TOPOLOGY SELECTION 8 2.2 PRINCIPLE OF OPERATION 11 2.2.1 BASIC OPERATION IN CCM 12 2.2.2 BASIC OPERATION IN DCM 15 2.3 OPERATION MODE 17 2.4 OVERALL ARCHITECTURE 19 CHAPTER 3 OPTIMAL INDUCTOR CURRENT CONTROLS FOR MAXIMUM ENERGY DELIVERY 23 3.1 CONSTANT INDUCTOR CURRENT CONTROL WITH SWITCHING-BASED STEPWISE CAPACITOR CHARGING SCHEME 24 3.1.1 CONVENTIONAL CHARGING SCHEME WITH A SWITCH 24 3.1.2 ADIABATIC STEPWISE CHARGING 27 3.1.3 PROPOSED START-UP SCHEME 29 3.2 CONSTANT INDUCTOR PEAK CURRENT CONTROL WITH VARIABLE ON-TIME PFM SCHEME 35 3.2.1 BASIC OPERATION OF PFM BUCK CONVERTER 35 3.2.2 CONSTANT ON-TIME PFM SCHEME 39 3.2.3 VARIABLE ON-TIME PFM SCHEME 41 3.3 INDUCTOR CURRENT PREDICTION WITH ADAP-TIVE OFF-TIME POSITIONING ZCD (AOP-ZCD) 44 3.3.1 PREVIOUS SAMPLING-BASED ZCD 44 3.3.2 PROPOSED ADAPTIVE OFF-TIME POSITIONING ZCD 47 CHAPTER 4 CIRCUIT IMPLEMENTATION 49 4.1 CIRCUIT IMPLEMENTATION OF SWITCHING-BASED STEPWISE CAPACITOR CHARGER 49 4.1.1 VOLTAGE DETECTOR (VD) 50 4.1.2 DIGITAL PULSE WIDTH MODULATOR (DPWM) 52 4.1.3 PROGRAMMABLE DUTY-CYCLE CONTROLLER (DCC) 55 4.1.4 SWITCHED CAPACITOR (SC) STEP-DOWN CONVERTER 57 4.2 CIRCUIT IMPLEMENTATION OF VARIABLE ON-TIME PULSE GENERATOR 59 4.3 CIRCUIT IMPLEMENTATION OF ADAPTIVE OFF-TIME POSITIONING ZCD 64 4.3.1 ADAPTIVE OFF-TIME (AOT) PULSE GENERATOR 64 4.3.2 TIMING ERROR DETECTOR AND SHIFT-REGISTER 68 CHAPTER 5 MEASUREMENT RESULTS OF PROPOSED BUCK CONVERTER 70 5.1 SWITCHING-BASED STEPWISE CAPACITOR CHARGER 71 5.2 STEADY-STATE PERFORMANCE WITH VOT PULSE GENERATOR AND AOP-ZCD 74 CHAPTER 6 REALIZATION OF BATTERY-FREE WIRELESS REMOTE SWITCH 84 6.1 KEY BUILDING BLOCKS OF BATTERY-FREE WIRELESS REMOTE SWITCH 85 6.2 PIEZOELECTRIC ENERGY HARVESTER WITH P-SSHI RECTIFIER 86 6.2.1 ANALYSIS ON SINGLE-PULSED ENERGY HARVESTING 88 6.2.2 PROPOSED PIEZOELECTRIC ENERGY HARVESTER 91 6.2.3 CIRCUIT IMPLEMENTATION 93 6.3 MEASUREMENT RESULTS OF BATTERY-FREE WIRELESS SWITCH 96 CHAPTER 7 CONCLUSION 101 BIBLIOGRAPHY 103 초 록 110Docto

A Biofuel-Cell-Based Energy Harvester With 86% Peak Efficiency and 0.25-V Minimum Input Voltage Using Source-Adaptive MPPT

This article presents an efficient cold-starting energy harvester system, fabricated in 65-nm CMOS. The proposed harvester uses no external electrical components and is compatible with biofuel-cell (BFC) voltage and power ranges. A power-efficient system architecture is proposed to keep the internal circuitry operating at 0.4 V while regulating the output voltage at 1 V using switched-capacitor dc–dc converters and a hysteretic controller. A startup enhancement block is presented to facilitate cold startup with any arbitrary input voltage. A real-time on-chip 2-D maximum power point tracking with source degradation tracing is also implemented to maintain power efficiency maximized over time. The system performs cold startup with a minimum input voltage of 0.39 V and continues its operation if the input voltage degrades to as low as 0.25 V. Peak power efficiency of 86% is achieved at 0.39 V of input voltage and 1.34 μW of output power with 220 nW of average power consumption of the chip. The end-to-end power efficiency is kept above 70% for a wide range of loading powers from 1 to 12 μW. The chip is integrated with a pair of lactate BFC electrodes with 2 mm of diameter on a prototype-printed circuit board (PCB). Integrated operation of the chip with the electrodes and a lactate solution is demonstrated

Modeling and Control of a 7-Level Switched Capacitor Rectifier for Wireless Power Transfer Systems

Wireless power continues to increase in popularity for consumer device charging. Rectifier characteristics like efficiency, compactness, impedance tunability, and harmonic content make the multi-level switched capacitor rectifier (MSC) an exceptional candidate for modern WPT systems. The MSC shares the voltage conversion characteristics of a post-rectification buck-boost topology, reduces waveform distortion via its multi-level modulation scheme, demonstrates tank tunability via the phase control inherent to actively switched rectifiers, and accomplishes all this without a bulky filter inductor. In this work, the MSC WPT system operation is explained, and a loss model is constructed. A prototype system is used to validate the models, showing exceptional agreement with the predicted efficiencies. The modeled MSC efficiencies are between 96.1% and 98.0% over the experimental power range up to 20.0 W. Two significant control loops are required for the MSC to be implemented in a real system. First, the output power is regulated using the modulation of the rectifier\u27s input voltage. Second, the switching frequency of the rectifier must exactly match the WPT carrier frequency set by the inverter on the primary side. Here, a small signal discrete time model is used to construct four transfer functions relating to the output voltage. Then, four novel time-to-time transfer functions are built on top of the discrete time model to inform the frequency synchronization feedback loop. Both loops are tested and validated in isolation. Finally, the dual-loop control problem is defined, closed form equations that include loop interactions are derived, and stable wide-range dual-loop operation is demonstrated experimentally

High Performance Power Management Integrated Circuits for Portable Devices

abstract: Portable devices often require multiple power management IC (PMIC) to power different sub-modules, Li-ion batteries are well suited for portable devices because of its small size, high energy density and long life cycle. Since Li-ion battery is the major power source for portable device, fast and high-efficiency battery charging solution has become a major requirement in portable device application. In the first part of dissertation, a high performance Li-ion switching battery charger is proposed. Cascaded two loop (CTL) control architecture is used for seamless CC-CV transition, time based technique is utilized to minimize controller area and power consumption. Time domain controller is implemented by using voltage controlled oscillator (VCO) and voltage controlled delay line (VCDL). Several efficiency improvement techniques such as segmented power-FET, quasi-zero voltage switching (QZVS) and switching frequency reduction are proposed. The proposed switching battery charger is able to provide maximum 2 A charging current and has an peak efficiency of 93.3%. By configure the charger as boost converter, the charger is able to provide maximum 1.5 A charging current while achieving 96.3% peak efficiency. The second part of dissertation presents a digital low dropout regulator (DLDO) for system on a chip (SoC) in portable devices application. The proposed DLDO achieve fast transient settling time, lower undershoot/overshoot and higher PSR performance compared to state of the art. By having a good PSR performance, the proposed DLDO is able to power mixed signal load. To achieve a fast load transient response, a load transient detector (LTD) enables boost mode operation of the digital PI controller. The boost mode operation achieves sub microsecond settling time, and reduces the settling time by 50% to 250 ns, undershoot/overshoot by 35% to 250 mV and 17% to 125 mV without compromising the system stability.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Ultra-Low-Power Sensors and Receivers for IoT Applications

The combination of ultra-low power analog front-ends and CMOS-compatible transducers enable new applications, such as environmental monitors, household appliances, health trackers, etc. that are seamlessly integrated into our daily lives. Furthermore, wireless connectivity allows many of these sensors to operate both independently and collectively. These techniques collectively fulfil the recent surge of internet-of-things (IoT) applications that have the potential to fundamentally change daily life for millions of people.In this dissertation, the circuit and system design of wireless receivers and sensors is presented that explores the challenges of implementing long lifespan, high accuracy, and large coverage range IoT sensor networks. The first is a wake-up receiver (WuRX), which continuously monitors the RF environment to wake up a higher-power radio upon detection of a predetermined RF signature. This work both improves sensitivity and reduces power over prior art through a multi-faceted design featuring an impedance transformation network with large passive voltage gain, an active envelope detector with high input impedance to facilitate large passive voltage gain, a low-power precision comparator, and a low-leakage digital baseband correlator.Although pushing the prior WuRX performance boundary by orders of magnitude, the first work shows moderate sensitivity, inferior temperature robustness, and large area with external lumped components. Thus, the second work shows a miniaturized WuRX that is temperature-compensated, yet still consumes only nano-watt power and millimeter area while operating at 9 GHz. To further reduce the area, a global common-mode feedback is utilized across the envelope detector and baseband amplifier that eliminates the need for off-chip ac-coupling components. Multiple temperature-compensation techniques are proposed to maintain constant bandwidth of the signal path and constant clock frequency. Both WuRXs operate at 0.4 V supply, consume near-zero power and achieve ~-70 dBm sensitivity.Lastly, the first reported CMOS 2-in-1 relative humidity and temperature sensor is presented. A unified analog front-end interfaces on-chip transducers and converts the inputs into a frequency vis a high-linearity frequency-locked loop. An incomplete-settling switched-capacitor-based Wheatstone bridge is proposed to sense the inputs in a power-efficient fashion