Efficient Dual Output Regulating Rectifier and Adiabatic Charge Pump for Biomedical Applications Employing Wireless Power Transfer †

A power management unit (PMU) is an essential block for diversified multi-functional low-power Internet of Things (IoT) and biomedical electronics. This paper includes a theoretical analysis of a high current, single-stage ac-dc, reconfigurable, dual output, regulating rectifier consisting of pulse width modulation (PWM) and pulse frequency modulation (PFM). The regulating rectifier provides two independently regulated supply voltages of 1.8 V and 3.3 V from an input ac voltage. The PFM control feedback consists of feedback-driven regulation to adjust the driving frequency of the power transistors through adaptive buffers in the active rectifier. The PWM/PFM mode control provides a feedback loop to adjust the conduction duration accurately and minimize power losses. The design also includes an adiabatic charge pump (CP) to provide a higher voltage level. The adiabatic CP consists of latch-up and power-saving topologies to enhance its power efficiency. Simulation results show that the dual regulating rectifier has 94.3% voltage conversion efficiency with an ac input magnitude of 3.5 Vp. The power conversion efficiency of the regulated 3.3 V output voltage is 82.3%. The adiabatic CP has an overall voltage conversion efficiency (VCE) of 92.9% with a total on-chip capacitance of 60 pF. The circuit was designed using 180 nm CMOS technology

Power conversion techniques in nanometer CMOS for low-power applications

As System-on-Chip (SoCs) in nanometer CMOS technologies grow larger, the power management process within these SoCs becomes very challenging. In the heart of this process lies the challenge of implementing energy-efficient and cost-effective DC-DC power converters. To address this challenge, this thesis studies in details three different aspects of DC-DC power converters and proposes potential solutions. First, to maximize power conversion efficiency, loss mechanisms must be studied and quantified. For that purpose, we provide comprehensive analysis and modeling of the various switching and conduction losses in low-power synchronous DC-DC buck converters in both Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM) operation, including the case with non-rail gate control of the power switches. Second, a DC-DC buck converter design with only on-chip passives is proposed and implemented in 65-nm CMOS technology. The converter switches at 588 MHz and uses a 20-nH and 300-pF on-chip inductor and capacitor respectively, and provides up to 30-mA of load at an output voltage in the range of 0.8-1.2 V. The proposed design features over 10% improvement in power conversion efficiency over a corresponding linear regulator while preserving low-cost implementation. Finally, a 40-mA buck converter design operating in the inherently-stable DCM mode for the entire load range is presented. It employs a Pulse Frequency Modulation (PFM) scheme using a Hysteretic-Assisted Adaptive Minimum On-Time (HA-AMOT) controller to automatically adapt to a wide range of operating scenarios while minimizing inductor peak current. As a result, compact silicon area, low quiescent current, high efficiency, and robust performance across all conditions can be achieved without any calibration

Improved Accuracy Area Efficient Hybrid CMOS/GaN DC-DC Buck Converterfor High Step-Down Ratio Applications

abstract: Point of Load (POL) DC-DC converters are increasingly used in space applications, data centres, electric vehicles, portable computers and devices and medical electronics. Heavy computing and processing capabilities of the modern devices have ushered the use of higher battery supply voltage to increase power storage. The need to address this consumer experience driven requirement has propelled the evolution of the next generation of small form-factor power converters which can operate with higher step down ratios while supplying heavy continuous load currents without sacrificing efficiency. Constant On-Time (COT) converter topology is capable of achieving stable operation at high conversion ratio with minimum off-chip components and small silicon area. This work proposes a Constant On-Time buck dc-dc converter for a wide dynamic input range and load currents from 100mA to 10A. Accuracy of this ripple based converter is improved by a unique voltage positioning technique which modulates the reference voltage to lower the average ripple profile close to the nominal output. Adaptive On-time block features a transient enhancement scheme to assist in faster voltage droop recovery when the output voltage dips below a defined threshold. UtilizingGallium Nitride (GaN) power switches enable the proposed converter to achieve very high efficiency while using smaller size inductor-capacitor (LC) power-stage. Use of novel Superjunction devices with higher drain-source blocking voltage simplifies the complex driver design and enables faster frequency of operation. It allows 1.8VComplementary Metal-Oxide Semiconductor (CMOS) devices to effectively drive GaNpower FETs which require 5V gate signal swing. The presented controller circuit uses internal ripple generation which reduces reliance on output cap equivalent series resistance (ESR) for loop stability and facilitates ripples reduction at the output. The ripple generation network is designed to provide ai optimally stable performance while maintaining load regulation and line regulation accuracy withing specified margin. The chip with ts external Power FET package is proposed to be integrated on a printed circuit board for testing. The designed power converter is expected to operate under 200 MRad of a total ionising dose of radiation enabling it to function within large hadron collider at CERN and space satellite and probe missions.Dissertation/ThesisMasters Thesis Electrical Engineering 201

Integrated circuits for efficient power delivery using pulse-width-modulation

Circuits and architectures for efficient power delivery have become crucial in emerging smart systems. Switching power amplifiers (PA) are very attractive for such applications, because they exhibit better efficiency compared to linear PA designs, due to saturated operation. Switching PAs also allow for utilization of deep submicron CMOS technologies, due to which these designs can be easily integrated with digital circuits, and can benefit from process scaling, in performance as well as in area. Pulse-width-modulation (PWM) is commonly used with switching PAs. A PWM signal typically employs a high-frequency switching pulse waveform as a carrier signal, wherein the pulse-width or duty-cycle of each pulse is modulated by a given low-frequency input signal. The carrier frequency can vary from several kHz to GHz, and is typically determined by the target application. In this thesis, efficient power-delivery circuits that use PWM with switching class-D stages are presented. Advanced circuit techniques, as well as architectures for PWM are proposed to enhance efficiency and circumvent the limitations of conventional architectures. A digitally-intensive transmitter using RF-PWM with a class-D PA is described in the first part of the thesis. The use of carrier switching for alleviating the dynamic range limitation that can be observed in classical RF-PWM implementations is introduced. The approach employs the full carrier frequency for half of the amplitude range, and the second harmonic of half of the carrier frequency, for the remainder of the amplitude range. This concept not only allows the transmitter to drive modulated signals with large peak-to-average power ratio (PAPR), but also improves the back-off efficiency due to reduced switching losses in the half carrier-frequency mode. A glitch-free phase selector is proposed that removes the deleterious glitches that can occur at the input data transitions. The phase-selector also prevents D flip-flop setup-and-hold time violations. The transmitter has been implemented in a 130-nm CMOS process. The measured peak output power and power-added-efficiency (PAE) are 25.6 dBm and 34%, respectively. While driving 802.11g 20-MHz 64-QAM OFDM signals, the average measured output power is 18.3 dBm and the PAE is 16%, with an EVM of -25.5 dB. The second part of the thesis describes a high-speed driver that provides a PWM output using a class-D PA. A PLL-based architecture is employed which eliminates the requirement for a precise ramp or triangular signal generator, and a high-speed comparator, which are typically used for PWM generation. Multi-level signaling is proposed to enhance back-off as well as peak efficiency, which is critical for signals with high PAPR. A differential, folded PWM scheme is introduced to achieve highly linear operation. 3-level operation is achieved without the requirement for additional supply source or sink paths, while 5-level operation is achieved with additional supply source and sink paths, compared to 2-level operation. The PWM driver has been implemented in a 130-nm CMOS process and can operate with a switching frequency of 40-to-170 MHz. For 2/3/5-level PA operation, with a 500 kHz sinusoidal input and 60 MHz switching frequency, the measured THD is -61/-62/-53 dB and corresponding efficiency is 71/83/86% with 175/200/220 mW output power level, respectively. Performance has also been verified for 2/3-level PA operation with a high PAPR signal with 500 kHz bandwidth. While intended as a general purpose amplifier, the approach is well-suited for applications such as power-line communications (PLC). The final part of the thesis introduces an efficient buck/buck-boost reconfigurable LED driver that supports PWM and PFM operation. The driver is based on peak current control. Rectified sin as well as sin² functions are employed in the reference signal to improve the power factor (PF) and total harmonic distortion (THD) of the buck and buck-boost converters. The design ensures that the peak of the inductor current maintains a constant level that is invariant for different AC line voltages. The operating mode of the design can be changed between PWM and PFM. The LED driver has been implemented in a 130-nm CMOS process. PF and THD are improved when the proposed reference is employed, and peak PF and lowest THD are 0.995/0.983/0.996 and 7.8/6.2/3.5% for the buck (PWM), buck (PFM), buck-boost (PFM) cases, respectively. The corresponding peak efficiency for the three cases is 88/92/91%, respectively.Electrical and Computer Engineerin

A PWM/PFM Dual-Mode DC-DC Buck Converter with Load-Dependent Efficiency-Controllable Scheme for Multi-Purpose IoT Applications

This paper presents a dual-mode DC-DC buck converter including a load-dependent, efficiency-controllable scheme to support multi-purpose IoT applications. For light-load applications, a selectable adaptive on-time pulse frequency modulation (PFM) control is proposed to achieve optimum power efficiency by selecting the optimum switching frequency according to the load current, thereby reducing unnecessary switching losses. When the inductor peak current value or converter output voltage ripple are considered in some applications, its on-time can be adjusted further. In heavy-load applications, a conventional pulse width modulation (PWM) control scheme is adopted, and its gate driver is structured to reduce dynamic current, preventing the current from shooting through the power switch. A proposed dual-mode buck converter prototype is fabricated in a 180 nm CMOS process, achieving its measured maximum efficiency of 95.7% and power density of 0.83 W/mm(2)

Optimal inductor current in boost DC/DC converters operating in burst mode under light-load conditions

This letter analyzes how the efficiency of boost dc/dc converters operating in burst mode under light-load conditions can be improved by an appropriate selection of the inductor current that transfers energy from the input to the output. A theoretical analysis evaluates the main power losses (fixed, conduction, and switching losses) involved in such converters, and how do they depend on the inductor current. This analysis shows that there is an optimal value of this current that causes minimum losses and, hence, maximum efficiency. These theoretical predictions are then compared with experimental data resulting from a commercial boost dc/dc converter (TPS61252), whose average inductor current is adjustable. Experimental results show that the use of the optimal inductor current, which was around 340 mA for an output voltage of 5 V, provides an efficiency increase of 7%.Peer ReviewedPostprint (author's final draft

A Study on Energy-Efficient Inductor Current Controls for Maximum Energy Delivery in Battery-free Buck Converter

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2017. 2. 김재하.A discontinuous conduction mode (DCM) buck converter, which acts as a voltage regulator in battery-free applications, is proposed to maximize the ener-gy delivery to the load system. In this work, we focus the energy loss problem during start-up and steady-state operation of the buck converter, which severely limits the energy delivery. Especially, the energy loss problem arises from the fact that there is no constant power source such as a battery and the only a small amount of energy harvested from the ambient energy sources is available. To address such energy loss problem, this dissertation proposes optimal induc-tor current control techniques at each operation to greatly reduce the energy losses. First, a switching-based stepwise capacitor charging scheme is presented that can charge the output capacitor with constant inductor current during start-up operation. By switching the inductor with gradually incrementing duty-cycle ratios in a stepwise fashion, the buck converter can make the inductor current a constant current source, which can greatly reduce the start-up energy loss com-pared to that in the conventional capacitor charging scheme with a voltage source. Second, a variable on-time (VOT) pulse-frequency-modulation (PFM) scheme is presented that can keep the peak inductor current constant during steady-state operation. By adaptively varying the on-time according to the op-erating voltage conditions of the buck converter, it can suppress the voltage ripple and improve the power efficiency even with a small output capacitor. Third, an adaptive off-time positioning zero-crossing detector (AOP-ZCD) is presented that can adaptively position the turn-off timing of the low-side switch close to the zero-inductor-current timing by predicting the inductor current waveform without using a power-hungry continuous-time ZCD. To demonstrate the proposed design concepts, the prototype battery-free wireless remote switch including the piezoelectric energy harvester and the proposed buck converter was fabricated in a 250 nm high-voltage CMOS technology. It can harvest a total energy of 246 μJ from a single button press action of a 300-mm2 lead magnesium niobate-lead titanate (PMN-PT) piezoelectric disc, and deliver more than 200 μJ to the load, which is sufficient to transmit a 4-byte-long message via 2.4-GHz wireless USB channel over a 10-m distance. If such battery-free application does not use the proposed buck converter, the energy losses in-curred at the buck converter would be larger than the energy harvested, and therefore it cannot operate with a single button-pressing action. Furthermore, thanks to the proposed energy efficient buck converter, the battery-free wire-less remote switch can be realized by using a cheaper PZT piezoelectric source, which can achieve a 10× cost reduction.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS CONTRIBUTION AND ORGANIZATION 6 CHAPTER 2 OPERATION MODE AND OVERALL ARCHITECTURE 8 2.1 TOPOLOGY SELECTION 8 2.2 PRINCIPLE OF OPERATION 11 2.2.1 BASIC OPERATION IN CCM 12 2.2.2 BASIC OPERATION IN DCM 15 2.3 OPERATION MODE 17 2.4 OVERALL ARCHITECTURE 19 CHAPTER 3 OPTIMAL INDUCTOR CURRENT CONTROLS FOR MAXIMUM ENERGY DELIVERY 23 3.1 CONSTANT INDUCTOR CURRENT CONTROL WITH SWITCHING-BASED STEPWISE CAPACITOR CHARGING SCHEME 24 3.1.1 CONVENTIONAL CHARGING SCHEME WITH A SWITCH 24 3.1.2 ADIABATIC STEPWISE CHARGING 27 3.1.3 PROPOSED START-UP SCHEME 29 3.2 CONSTANT INDUCTOR PEAK CURRENT CONTROL WITH VARIABLE ON-TIME PFM SCHEME 35 3.2.1 BASIC OPERATION OF PFM BUCK CONVERTER 35 3.2.2 CONSTANT ON-TIME PFM SCHEME 39 3.2.3 VARIABLE ON-TIME PFM SCHEME 41 3.3 INDUCTOR CURRENT PREDICTION WITH ADAP-TIVE OFF-TIME POSITIONING ZCD (AOP-ZCD) 44 3.3.1 PREVIOUS SAMPLING-BASED ZCD 44 3.3.2 PROPOSED ADAPTIVE OFF-TIME POSITIONING ZCD 47 CHAPTER 4 CIRCUIT IMPLEMENTATION 49 4.1 CIRCUIT IMPLEMENTATION OF SWITCHING-BASED STEPWISE CAPACITOR CHARGER 49 4.1.1 VOLTAGE DETECTOR (VD) 50 4.1.2 DIGITAL PULSE WIDTH MODULATOR (DPWM) 52 4.1.3 PROGRAMMABLE DUTY-CYCLE CONTROLLER (DCC) 55 4.1.4 SWITCHED CAPACITOR (SC) STEP-DOWN CONVERTER 57 4.2 CIRCUIT IMPLEMENTATION OF VARIABLE ON-TIME PULSE GENERATOR 59 4.3 CIRCUIT IMPLEMENTATION OF ADAPTIVE OFF-TIME POSITIONING ZCD 64 4.3.1 ADAPTIVE OFF-TIME (AOT) PULSE GENERATOR 64 4.3.2 TIMING ERROR DETECTOR AND SHIFT-REGISTER 68 CHAPTER 5 MEASUREMENT RESULTS OF PROPOSED BUCK CONVERTER 70 5.1 SWITCHING-BASED STEPWISE CAPACITOR CHARGER 71 5.2 STEADY-STATE PERFORMANCE WITH VOT PULSE GENERATOR AND AOP-ZCD 74 CHAPTER 6 REALIZATION OF BATTERY-FREE WIRELESS REMOTE SWITCH 84 6.1 KEY BUILDING BLOCKS OF BATTERY-FREE WIRELESS REMOTE SWITCH 85 6.2 PIEZOELECTRIC ENERGY HARVESTER WITH P-SSHI RECTIFIER 86 6.2.1 ANALYSIS ON SINGLE-PULSED ENERGY HARVESTING 88 6.2.2 PROPOSED PIEZOELECTRIC ENERGY HARVESTER 91 6.2.3 CIRCUIT IMPLEMENTATION 93 6.3 MEASUREMENT RESULTS OF BATTERY-FREE WIRELESS SWITCH 96 CHAPTER 7 CONCLUSION 101 BIBLIOGRAPHY 103 초 록 110Docto

Design of Low-Cost Energy Harvesting and Delivery Systems for Self-Powered Devices: Application to Authentication IC

This thesis investigates the development of low-cost energy harvesting and delivery systems for low-power low-duty-cycle devices. Initially, we begin by designing a power management scheme for on-demand power delivery. The baseline implementation is also used to identify critical challenges for low-power energy harvesting. We further propose a robust self-powered energy harvesting and delivery system (EHDS) design as a solution to achieve energy autonomy in standalone systems. The design demonstrates a complete ecosystem for low-overhead pulse-frequency modulated (PFM) harvesting while reducing harvesting window confinement and overall implementation footprint. Two transient-based models are developed for improved accuracy during design space exploration and optimization for both PFM power conversion and energy harvesting. Finally, a low-power authentication IC is demonstrated and projected designs for self-powered System-on-Chips (SoCs) are presented. The proposed designs are proto-typed in two test-chips in a 65nm CMOS process and measurement data showcase improved performance in terms of battery power, cold-start duration, passives (inductance and capacitance) needed, and end-to-end harvesting/conversion efficiency.Ph.D

Analysis and design of a wide dynamic range pulse-frequency modulation CMOS image sensor

Complementary Metal-Oxide Semiconductor (CMOS) image sensor is the dominant electronic imaging device in many application fields, including the mobile or portable devices, teleconference cameras, surveillance and medical imaging sensors. Wide dynamic range (WDR) imaging is of interest particular, demonstrating a large-contrast imaging range of the sensor. As of today, different approaches have been presented to provide solutions for this purpose, but there exists various trade-offs among these designs, which limit the number of applications. A pulse-frequency modulation (PFM) pixel offers the possibility to outperform existing designs in WDR imaging applications, however issues such as uniformity and cost have to be carefully handled to make it practical for different purposes. In addition, a complete evaluation of the sensor performance has to be executed prior to fabrication in silicon technology. A thorough investigation of WDR image sensor based on the PFM pixel is performed in this thesis. Starting with the analysis, modeling, and measurements of a PFM pixel, the details of every particular circuit operation are presented. The causes of dynamic range (DR) limitations and signal nonlinearity are identified, and noise measurement is also performed, to guide future design strategies. We present the design of an innovative double-delta compensating (DDC) technique which increases the sensor uniformity as well as DR. This technique achieves performance optimization of the PFM pixel with a minimal cost an improved linearity, and is carefully simulated to demonstrate its feasibility. A quad-sampling technique is also presented with the cooperation of pixel and column circuits to generate a WDR image sensor with a reduced cost for the pixel. This method, which is verified through the field-programmable gate array (FPGA) implementation, saves considerable area in the pixel and employs the maximal DR that a PFM pixel provides. A complete WDR image sensor structure is proposed to evaluate the performance and feasibility of fabrication in silicon technology. The plans of future work and possible improvements are also presented

A Fast Response Dual Mode Buck Converter with Automatic Mode Transition

Dual mode DC-DC converters utilizing PWM and PFM modes of operation have been widely used to improve the efficiency over a wide range of the load current. Due to the highly varying nature of the load, it is beneficial to have the converter switch between the modes without an external mode select signal. This work proposes a new technique for automatic mode switching which maintains very high efficiency at light loads and at the same time, keeps the output well regulated during a load transient from sleep to the active state. The Constant On-time PFM scheme and a zero current detector avoids the use of an accurate current sensing block. The power supply rejection is also improved using feed-forward paths from the supply in both the PWM and PFM modes. A new implementation of the PWM controller with clamped error voltage required to meet the specifications is also shown. The proposed feedback implementation using a programmable current source and resistance provides smooth output programming