MURAC: A unified machine model for heterogeneous computers

Includes bibliographical referencesHeterogeneous computing enables the performance and energy advantages of multiple distinct processing architectures to be efficiently exploited within a single machine. These systems are capable of delivering large performance increases by matching the applications to architectures that are most suited to them. The Multiple Runtime-reconfigurable Architecture Computer (MURAC) model has been proposed to tackle the problems commonly found in the design and usage of these machines. This model presents a system-level approach that creates a clear separation of concerns between the system implementer and the application developer. The three key concepts that make up the MURAC model are a unified machine model, a unified instruction stream and a unified memory space. A simple programming model built upon these abstractions provides a consistent interface for interacting with the underlying machine to the user application. This programming model simplifies application partitioning between hardware and software and allows the easy integration of different execution models within the single control ow of a mixed-architecture application. The theoretical and practical trade-offs of the proposed model have been explored through the design of several systems. An instruction-accurate system simulator has been developed that supports the simulated execution of mixed-architecture applications. An embedded System-on-Chip implementation has been used to measure the overhead in hardware resources required to support the model, which was found to be minimal. An implementation of the model within an operating system on a tightly-coupled reconfigurable processor platform has been created. This implementation is used to extend the software scheduler to allow for the full support of mixed-architecture applications in a multitasking environment. Different scheduling strategies have been tested using this scheduler for mixed-architecture applications. The design and implementation of these systems has shown that a unified abstraction model for heterogeneous computers provides important usability benefits to system and application designers. These benefits are achieved through a consistent view of the multiple different architectures to the operating system and user applications. This allows them to focus on achieving their performance and efficiency goals by gaining the benefits of different execution models during runtime without the complex implementation details of the system-level synchronisation and coordination

Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking

With the help of the parallelism provided by the fine-grained architecture, hardware accelerators on Field Programmable Gate Arrays (FPGAs) can significantly improve the performance of many applications. However, designers are required to have excellent hardware programming skills and unique optimization techniques to explore the potential of FPGA resources fully. Intermediate frameworks above hardware circuits are proposed to improve either performance or productivity by leveraging parallel programming models beyond the multi-core era. In this work, we propose the PolyPC (Polymorphic Parallel Computing) framework, which targets enhancing productivity without losing performance. It helps designers develop parallelized applications and implement them on FPGAs. The PolyPC framework implements a custom hardware platform, on which programs written in an OpenCL-like programming model can launch. Additionally, the PolyPC framework extends vendor-provided tools to provide a complete development environment including intermediate software framework, and automatic system builders. Designers\u27 programs can be either synthesized as hardware processing elements (PEs) or compiled to executable files running on software PEs. Benefiting from nontrivial features of re-loadable PEs, and independent group-level schedulers, the multitasking is enabled for both software and hardware PEs to improve the efficiency of utilizing hardware resources. The PolyPC framework is evaluated regarding performance, area efficiency, and multitasking. The results show a maximum 66 times speedup over a dual-core ARM processor and 1043 times speedup over a high-performance MicroBlaze with 125 times of area efficiency. It delivers a significant improvement in response time to high-priority tasks with the priority-aware scheduling. Overheads of multitasking are evaluated to analyze trade-offs. With the help of the design flow, the OpenCL application programs are converted into executables through the front-end source-to-source transformation and back-end synthesis/compilation to run on PEs, and the framework is generated from users\u27 specifications

Parallel and Distributed Computing

The 14 chapters presented in this book cover a wide variety of representative works ranging from hardware design to application development. Particularly, the topics that are addressed are programmable and reconfigurable devices and systems, dependability of GPUs (General Purpose Units), network topologies, cache coherence protocols, resource allocation, scheduling algorithms, peertopeer networks, largescale network simulation, and parallel routines and algorithms. In this way, the articles included in this book constitute an excellent reference for engineers and researchers who have particular interests in each of these topics in parallel and distributed computing

Multi-core architectures with coarse-grained dynamically reconfigurable processors for broadband wireless access technologies

Broadband Wireless Access technologies have significant market potential, especially the WiMAX protocol which can deliver data rates of tens of Mbps. Strong demand for high performance WiMAX solutions is forcing designers to seek help from multi-core processors that offer competitive advantages in terms of all performance metrics, such as speed, power and area. Through the provision of a degree of flexibility similar to that of a DSP and performance and power consumption advantages approaching that of an ASIC, coarse-grained dynamically reconfigurable processors are proving to be strong candidates for processing cores used in future high performance multi-core processor systems. This thesis investigates multi-core architectures with a newly emerging dynamically reconfigurable processor – RICA, targeting WiMAX physical layer applications. A novel master-slave multi-core architecture is proposed, using RICA processing cores. A SystemC based simulator, called MRPSIM, is devised to model this multi-core architecture. This simulator provides fast simulation speed and timing accuracy, offers flexible architectural options to configure the multi-core architecture, and enables the analysis and investigation of multi-core architectures. Meanwhile a profiling-driven mapping methodology is developed to partition the WiMAX application into multiple tasks as well as schedule and map these tasks onto the multi-core architecture, aiming to reduce the overall system execution time. Both the MRPSIM simulator and the mapping methodology are seamlessly integrated with the existing RICA tool flow. Based on the proposed master-slave multi-core architecture, a series of diverse homogeneous and heterogeneous multi-core solutions are designed for different fixed WiMAX physical layer profiles. Implemented in ANSI C and executed on the MRPSIM simulator, these multi-core solutions contain different numbers of cores, combine various memory architectures and task partitioning schemes, and deliver high throughputs at relatively low area costs. Meanwhile a design space exploration methodology is developed to search the design space for multi-core systems to find suitable solutions under certain system constraints. Finally, laying a foundation for future multithreading exploration on the proposed multi-core architecture, this thesis investigates the porting of a real-time operating system – Micro C/OS-II to a single RICA processor. A multitasking version of WiMAX is implemented on a single RICA processor with the operating system support

Зменшення накладних видатків реконфігурації в реконфігурованих обчислювальних системах

Запропоновано нові засоби реконфігурації, що дозволяють мінімізувати накладні видатки реконфігурації, забезпечуючи підвищення продуктивності динамічно реконфігурованих обчислювальних систем. Запропонований метод повторного використання апаратних ресурсів функціональних блоків, забезпечує інтенсивне прискорення реконфігурації за рахунок видалення всієї непродуктивної складової часу реконфігурації.Предложены новые средства реконфигурации, которые позволяют минимизировать накладные расходы реконфигурации, обеспечивая повышение производительности динамически реконфигурируемых вычислительных систем. Предложенный метод повторного использования аппаратных ресурсов функциональных блоков обеспечивает интенсивнее ускорение реконфигурации за счет удаления всей непродуктивной составляющей времени реконфигурации.The new means of the reconfiguration is proposed that to minimize overheads reconfiguration and to provide improved performance dynamically reconfigurable systems. The proposed reusing hardware resources method of function blocks provides an intensive acceleration reconfiguration by removing all the overhead part-time reconfiguration

Формалізація адаптивного відображення задач у реконфігурованих обчислювальних системах на ПЛІС

Розроблено математичні моделі адаптивної реконфігурації, що визначають значення критеріїв ефективності реконфігурованих обчислень. Запропоновано новий підхід до скорочення критичного часу виконання паралельних алгоритмів за рахунок видалення непродуктивної складової часу реконфігурації з критичного шляху графу алгоритму. Розроблено та досліджено програмну модель запропонованих засобів адаптивного відображення алгоритму на реконфігуровану обчислювальну структуру на ПЛІС.Formal models of adaptive reconfiguration were developed. It allowed determining the value of the performance criteria of reconfigurable computing system. A new approach of reducing the critical execution time of parallel algorithms was proposed by removing reconfiguration time overheads from the critical path of algorithm`s graph. Program model of proposed means for adaptive tasks mapping on reconfigurable FPGA computing structur

A Reconfigurable Processor for Heterogeneous Multi-Core Architectures

A reconfigurable processor is a general-purpose processor coupled with an FPGA-like reconfigurable fabric. By deploying application-specific accelerators, performance for a wide range of applications can be improved with such a system. In this work concepts are designed for the use of reconfigurable processors in multi-tasking scenarios and as part of multi-core systems

Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC\u2710 - May 17-19, 2010 Karlsruhe, Germany. (KIT Scientific Reports ; 7551)

ReCoSoC is intended to be a periodic annual meeting to expose and discuss gathered expertise as well as state of the art research around SoC related topics through plenary invited papers and posters. The workshop aims to provide a prospective view of tomorrow\u27s challenges in the multibillion transistor era, taking into account the emerging techniques and architectures exploring the synergy between flexible on-chip communication and system reconfigurability

Метод забезпечення часових вимог якості обслуговування в реконфігурованих обчислювальних системах

The process of calculations control in reconfigurable computing systems characterized by the time constraints of both the applications solved and the functional and structural organization of the system is investigated.As part of this, the method is modified and mathematically substantiated for determining the time intervals of tasks. The proposed modification to the analysis of tasks acceleration index allows to evaluate the unproductive time expenditure taking into account the FPGA hardware limitations in the computer algorithms mapping to the reconfigurable computing structure.The method of providing time parameters of service quality in the reconfigurable computing system that provides given application runtime by determining the amount of unproductive time-consuming reconfiguration and the choice of optimal service discipline for each task in terms of time and existing hardware limitations was proposed. The use of the proposed method of determining the time intervals, which the implementation of the method is based on determining the sequence of tasks for which the target architecture of the computer system is effective and the use of additional mechanisms to reduce overhead does not speed up calculations within the advertised time requirements. Application of the proposed method allows to determine and optimize the impact of space limitations the reconfiguration time and reduce the number of rejections of tasks in the dynamic mapping of task flows to the reconfigurable computational structure. The formalization of the method for determining the time intervals of tasks was developed, for which the optimal boundaries of the effective use of the proposed facilities in terms of the adequacy of the offered application time limits to the limits of the reconfigurable computer system were defined and justified.The proposed tools can be used in modern high-performance reconfigurable computing systems during solving the problems of control of various technical and management processes and implementation of multidimensional calculations in complex information systems.Исследуется процесс управления вычислениями в реконфигурируемых вычислительных системах. Предложен метод обеспечения временных требований качества обслуживания, который обеспечивает требуемое время выполнения вычислительных алгоритмов с учетом ограничений реконфигурируемой вычислительной системы. Предложенный метод позволяет повысить эффективность процесса управления вычислительным процессом в реконфигурируемых вычислительных системах за счет выбора оптимального способа обслуживания для каждой задачи путем определения объема непроизводительных временных затратДосліджується процес управління обчисленнями в реконфігуровних обчислювальних системах. Запропонований метод забезпечення часових вимог якості обслуговування, який забезпечує затребуваний час виконання обчислювальних алгоритмів з врахуванням обмежень реконфігуровної обчислювальної системи. Запропонований метод дозволяє підвищити ефективність процесу управління обчислювальним процесом в реконфігуровних обчислювальних системах за рахунок вибору оптимального способу обслуговування для кожної задачі шляхом визначення обсягу непродуктивних часових витра