Adaptive Load Sharing for Network Processors

A novel scheme for processing packets in a router is presented, which provides for load sharing among multiple network processors distributed within the router. It is complemented by a feedback control mechanism designed to prevent processor overload. Incoming traffic is scheduled to multiple processors based on a deterministic mapping. The mapping formula is derived from the robust hash routing (also known as the highest random weight - HRW) scheme, introduced in K.W. Ross, IEEE Network, 11(6), 1997, and D.G. Thaler et al., IEEE Trans. Networking, 6(1), 1998. No state information on individual flow mapping needs to be stored, but for each packet, a mapping function is computed over an identifier vector, a predefined set of fields in the packet. An adaptive extension to the HRW scheme is provided in order to cope with biased traffic patterns. We prove that our adaptation possesses the minimal disruption property with respect to the mapping and exploit that property in order to minimize the probability of flow reordering. Simulation results indicate that the scheme achieves significant improvements in processor utilization. A higher number of router interfaces can thus be supported with the same amount of processing power

Adaptive Load Sharing for Network Processors

A novel scheme for processing packets in a router is presented that provides load sharing among multiple network processors distributed within the router. It is complemented by a feedback control mechanism designed to prevent processor overload. Incoming traffic is scheduled to multiple processors based on a deterministic mapping. The mapping formula is derived from the robust hash routing (also known as the highest random weight - HRW) scheme, introduced in K.W.\ Ross, IEEE Network, 11(6), 1997, and D.G.\ Thaler et al., IEEE Trans.\ Networking, 6 (1), 1998. \emph{No state information} on individual flow mapping has to be stored, but for each packet, a mapping function is computed over an \emph{identifier vector}, a predefined set of fields in the packet. An \emph{adaptive extension} to the HRW scheme is provided to cope with biased traffic patterns. We prove that our adaptation possesses the \emph {minimal disruption property} with respect to the mapping and exploit that property to minimize the probability of flow reordering. Simulation results indicate that the scheme achieves significant improvements in processor utilization. A higher number of router interfaces can thus be supported with the same amount of processing power

Virtualization for a Network Processor Runtime System

The continuing ossification of the Internet is slowing the pace of network innovation. Network diversification presents one solution to this problem, by virtualizing the network at multiple layers. Diversified networks consist of a shared physical substrate, virtual routers (metarouters), and virtual links (metalinks). Virtualizing routers enables smooth and incremental upgrades to new network services. Our current priority for a diversified router prototype is to enable reserved slices of the network for researchers to perform repeatable, high-speed network experiments. General-purpose processors have well established techniques for virtualization, but do not scale efficiently to multi-gigabit speeds. To achieve these speeds, we employ network processors (NPs), typically consisting of multicore, multi-threaded processors with asymmetric, heterogeneous memories. The complexity and lack of hardware thread isolation in NP’s, combined with a lack of simple programming models, creates numerous challenges for effective sharing between metarouters. In this paper, we detail strategies for enabling NP virtualization at the link, memory, and processor levels, to better enable a research infrastructure for network innovation

Robust dynamic network traffic partitioning against malicious attacks

The continual growth of network traffic rates leads to heavy packet processing overheads, and a typical solution is to partition traffic into multiple network processors for parallel processing especially in emerging software-defined networks. This paper is thus motivated to propose a robust dynamic network traffic partitioning scheme to defend against malicious attacks. After introducing the conceptual framework of dynamic network traffic partitioning based on flow tables, we strengthen its TCP connection management by building a half-open connection separation mechanism to isolate false connections in the initial connection table (ICT). Then, the lookup performance of the ICT table is reinforced by applying counting bloom filters to cope with malicious behaviors such as SYN flooding attacks. Finally, we evaluate the performance of our proposed traffic partitioning scheme with real network traffic traces and simulated malicious traffic by experiments. Experimental results indicate that our proposed scheme outperforms the conventional ones in terms of packet distribution performance especially robustness against malicious attacks

Scalable and Adaptive Load Balancing on IBM PowerNP

Web and other Internet-based server farms are a critical company resource. A solution to the increased complexity of server farms and to the need to improve the server performance in terms of scalability, fault tolerance and management is to implement a load balancing technique. It consists of a front-end machine which intelligently redirects the traffic to several Real Servers. We discuss the feasibility of implementing adaptive load balancing with minimal flow disruption on the IBM PowerNP Network Processor. We focus our attention on the steady-state part of the algorithm and propose a PowerNP-tailored mapping algorithm derived from Robust Hash Mapping. We propose and show a fast algorithm solution (despite the simple arithmetical logic of the PowerNP), as well as a scalable approach (aiming at minimizing the packet processing time) and, finally, we present some initial performance results

A CAM-Based, High-Performance Classifier-Scheduler for a Video Network Processor.

Classification and scheduling are key functionalities of a network processor. Network processors are equipped with application specific integrated circuits (ASIC), so that as IP (Internet Protocol) packets arrive, they can be processed directly without using the central processing unit. A new network processor is proposed called the video network processor (VNP) for real time broadcasting of video streams for IP television (IPTV). This thesis explores the challenge in designing a combined classification and scheduling module for a VNP. I propose and design the classifier-scheduler module which will classify and schedule data for VNP. The proposed module discriminates between IP packets and video packets. The video packets are further processed for digital rights management (DRM). IP packets which carry regular traffic will traverse without any modification. Basic architecture of VNP and architecture of classifier-scheduler module based on content addressable memory (CAM) and random access memory (RAM) has been proposed. The module has been designed and simulated in Xilinx 9.1i; is built in ISE simulator with a throughput of 1.79 Mbps and a maximum working frequency of 111.89 MHz at a power dissipation of 33.6mW. The code has been translated and mapped for Spartan and Virtex family of devices

Load sharing for multiprocessor network nodes

This thesis discusses techniques for sharing the processing load among multiple processing units within systems that act as nodes in a data communications network. Load-sharing techniques have been explored in the field of computer science for many years and their benefits are well known, including better utilization of processing capacity and enhanced system fault tolerance. We discuss deploying such methods in the specifics of the networking environment. We concentrate particularly on the data plane, or the data packet-processing tasks. After reviewing the main results in the fields of load sharing and multiprocessor networking systems architectures, we conduct a preparatory optimization study of a router system to gain better understanding of the optimization issues in a particular multiprocessor system. The main contribution of this thesis, the adaptive load-sharing method, is presented next. We first formulate the optimization problem of mapping packets to processors. The goal is to minimize the likelihood of flow reordering, while respecting certain system constraints, such as the acceptable probability of a packet loss. As we show that the task is an NP-complete problem, we propose a heuristic method that uses an adaptive hash-based mapping to assign packets to processors. We demonstrate its advantages and prove that the method adaptation policy possesses the key minimal disruption property with respect to the mapping. In other words, the adaptation results in a minimum number of flows being moved among processing units. Further on, the method is validated in an extensive set of simulations designed to imitate the networking environment. Finally, two sample applications, an architecture of a multiprotocol router and an implementation of a server load balancer on a network processor demonstrate the applicability of the method

Investigation of parallel programming on heterogeneous multiprocessors

Multi-core processors have become ordinary in modern commodity computers. Computationally intensive applications, like video processing, that previously only ran on specialized hardware, are now common on home computers. However, the demand for more computing power is ever-increasing, and with the introduction of high definition video, more performance is desired. As an alternative to having multiple identical processor cores, heterogeneous multiprocessors have cores with different capabilities. This allows tasks to be processed on simple cores with specialized functionality. The simplicity furthers low power consumption, small die usage, and low price. Dealing with heterogeneous cores increases the complexity of writing programs for the architecture. The reasons for this includes different capabilities of the cores, and some heterogeneous architectures do not have shared memory. Without shared memory, accessing main memory requires explicit transfers to local memory. In this thesis, we consider two architectures, the STI Cell/B.E. and Intel IXP2400, and evaluate parallelization strategies and performance for real-world problems. Our tests show promising throughput for some applications, and we propose a scheme for offloading computationally intensive parts of an existing application

Load Balancing for the Agile All-Photonic Network

The Agile All-Photonic Network (AAPN) uses Time Division Multiplexing (TDM) to better utilize the bandwidth of Wavelength Division Multiplexing (WDM) systems. It uses agile all-photonic switches as advances in the photonic switching technology made the design of all-photonic devices with switching latency in the sub-microseconds feasible. The network has a simplified overlaid star architecture that can be deployed in a Metropolitan Area Network (MAN) or a Wide Area Network (WAN) environment. This overlaid architecture, as opposed to general mesh architecture, scales network capacity to multiples of Tera bits per second, simplif�ies routing, increases reliability, eliminates wavelength conversion, and the need for accurate traffic engineering. The objective of this thesis is to propose and analyze dif�ferent load balancing methods for the deployment of the AAPN network in a WAN environment. The analysis should provide interested Internet Service Providers (ISPs) with a comprehensive study of load balancing methods for using the AAPN network as their backbone network. The methods balance the load at the ow level to reduce packet reordering. The methods are stateless and can compute routes quickly based on the packet flow identi�er. This is an important issue when deploying AAPN as an Internet backbone network where the number of flows is large and storing ow state in lookup tables can limit the network performance. The load balancing methods, deployed at the edge nodes, require reliable signaling with the bandwidth schedulers at the core nodes. To provide a reliable channel between the edge and core nodes, the Control Messages Delivery Protocol (CMDP) is proposed as part of this thesis work. The protocol is designed to work in environments where propagation delays are long and/or the error rates are high. It is used to deliver a burst of short messages in sequence and with no errors. Combined with the reliable routing protocol proposed previously for the AAPN network, they form the control plane for the network. To extend the applicability of the load balancing methods to topologies beyond AAPN overlaid star topology, the Valiant Load Balancing (VLB) method is used to build an overlaid star topology on top of the physical network. The VLB method provides guaranteed performance for highly variable tra�c matrices within the hose traffic model constraints. In addition to the guaranteed performance, deploying the VLB method in the AAPN network, eliminates signaling and replaces the dynamic core schedulers with static scheduler that can accommodate all tra�c matrices within the hose tra�c model boundaries