Survey on Machine Learning Algorithms Enhancing the Functional Verification Process

The continuing increase in functional requirements of modern hardware designs means the traditional functional verification process becomes inefficient in meeting the time-to-market goal with sufficient level of confidence in the design. Therefore, the need for enhancing the process is evident. Machine learning (ML) models proved to be valuable for automating major parts of the process, which have typically occupied the bandwidth of engineers; diverting them from adding new coverage metrics to make the designs more robust. Current research of deploying different (ML) models prove to be promising in areas such as stimulus constraining, test generation, coverage collection and bug detection and localization. An example of deploying artificial neural network (ANN) in test generation shows 24.5× speed up in functionally verifying a dual-core RISC processor specification. Another study demonstrates how k-means clustering can reduce redundancy of simulation trace dump of an AHB-to-WHISHBONE bridge by 21%, thus reducing the debugging effort by not having to inspect unnecessary waveforms. The surveyed work demonstrates a comprehensive overview of current (ML) models enhancing the functional verification process from which an insight of promising future research areas is inferred

Automated Debugging Methodology for FPGA-based Systems

Electronic devices make up a vital part of our lives. These are seen from mobiles, laptops, computers, home automation, etc. to name a few. The modern designs constitute billions of transistors. However, with this evolution, ensuring that the devices fulfill the designer’s expectation under variable conditions has also become a great challenge. This requires a lot of design time and effort. Whenever an error is encountered, the process is re-started. Hence, it is desired to minimize the number of spins required to achieve an error-free product, as each spin results in loss of time and effort. Software-based simulation systems present the main technique to ensure the verification of the design before fabrication. However, few design errors (bugs) are likely to escape the simulation process. Such bugs subsequently appear during the post-silicon phase. Finding such bugs is time-consuming due to inherent invisibility of the hardware. Instead of software simulation of the design in the pre-silicon phase, post-silicon techniques permit the designers to verify the functionality through the physical implementations of the design. The main benefit of the methodology is that the implemented design in the post-silicon phase runs many order-of-magnitude faster than its counterpart in pre-silicon. This allows the designers to validate their design more exhaustively. This thesis presents five main contributions to enable a fast and automated debugging solution for reconfigurable hardware. During the research work, we used an obstacle avoidance system for robotic vehicles as a use case to illustrate how to apply the proposed debugging solution in practical environments. The first contribution presents a debugging system capable of providing a lossless trace of debugging data which permits a cycle-accurate replay. This methodology ensures capturing permanent as well as intermittent errors in the implemented design. The contribution also describes a solution to enhance hardware observability. It is proposed to utilize processor-configurable concentration networks, employ debug data compression to transmit the data more efficiently, and partially reconfiguring the debugging system at run-time to save the time required for design re-compilation as well as preserve the timing closure. The second contribution presents a solution for communication-centric designs. Furthermore, solutions for designs with multi-clock domains are also discussed. The third contribution presents a priority-based signal selection methodology to identify the signals which can be more helpful during the debugging process. A connectivity generation tool is also presented which can map the identified signals to the debugging system. The fourth contribution presents an automated error detection solution which can help in capturing the permanent as well as intermittent errors without continuous monitoring of debugging data. The proposed solution works for designs even in the absence of golden reference. The fifth contribution proposes to use artificial intelligence for post-silicon debugging. We presented a novel idea of using a recurrent neural network for debugging when a golden reference is present for training the network. Furthermore, the idea was also extended to designs where golden reference is not present

Productive Programming Systems for Heterogeneous Supercomputers

The majority of today's scientific and data analytics workloads are still run on relatively energy inefficient, heavyweight, general-purpose processing cores, often referred to in the literature as latency-oriented architectures. The flexibility of these architectures and the programmer aids included (e.g. large and deep cache hierarchies, branch prediction logic, pre-fetch logic) makes them flexible enough to run a wide range of applications fast. However, we have started to see growth in the use of lightweight, simpler, energy-efficient, and functionally constrained cores. These architectures are commonly referred to as throughput-oriented. Within each shared memory node, the computational backbone of future throughput-oriented HPC machines will consist of large pools of lightweight cores. The first wave of throughput-oriented computing came in the mid 2000's with the use of GPUs for general-purpose and scientific computing. Today we are entering the second wave of throughput-oriented computing, with the introduction of NVIDIA Pascal GPUs, Intel Knights Landing Xeon Phi processors, the Epiphany Co-Processor, the Sunway MPP, and other throughput-oriented architectures that enable pre-exascale computing. However, while the majority of the FLOPS in designs for future HPC systems come from throughput-oriented architectures, they are still commonly paired with latency-oriented cores which handle management functions and lightweight/un-parallelizable computational kernels. Hence, most future HPC machines will be heterogeneous in their processing cores. However, the heterogeneity of future machines will not be limited to the processing elements. Indeed, heterogeneity will also exist in the storage, networking, memory, and software stacks of future supercomputers. As a result, it will be necessary to combine many different programming models and libraries in a single application. How to do so in a programmable and well-performing manner is an open research question. This thesis addresses this question using two approaches. First, we explore using managed runtimes on HPC platforms. As a result of their high-level programming models, these managed runtimes have a long history of supporting data analytics workloads on commodity hardware, but often come with overheads which make them less common in the HPC domain. Managed runtimes are also not supported natively on throughput-oriented architectures. Second, we explore the use of a modular programming model and work-stealing runtime to compose the programming and scheduling of multiple third-party HPC libraries. This approach leverages existing investment in HPC libraries, unifies the scheduling of work on a platform, and is designed to quickly support new programming model and runtime extensions. In support of these two approaches, this thesis also makes novel contributions in tooling for future supercomputers. We demonstrate the value of checkpoints as a software development tool on current and future HPC machines, and present novel techniques in performance prediction across heterogeneous cores

Development of an Unsteady Aeroelastic Solver for the Analysis of Modern Turbomachinery Designs

Developers of aircraft gas turbine engines continually strive for greater efficiency and higher thrust-to-weight ratio designs. To meet these goals, advanced designs generally feature thin, low aspect airfoils, which offer increased performance but are highly susceptible to flow-induced vibrations. As a result, High Cycle Fatigue (HCF) has become a universal problem throughout the gas turbine industry and unsteady aeroelastic computational models are needed to predict and prevent these problems in modern turbomachinery designs. This research presents the development of a 3D unsteady aeroelastic solver for turbomachinery applications. To accomplish this, a well established turbomachinery Computational Fluid Dynamics (CFD) code called Corsair is loosely coupled to the commercial Computational Structural Solver (CSD) Ansys® through the use of a Fluid Structure Interaction (FSI) module. Significant modifications are made to Corsair to handle the integration of the FSI module and improve overall performance. To properly account for fluid grid deformations dictated by the FSI module, temporal based coordinate transformation metrics are incorporated into Corsair. Wall functions with user specified surface roughness are also added to reduce fluid grid density requirements near solid surfaces. To increase overall performance and ease of future modifications to the source code, Corsair is rewritten in Fortran 90 with an emphasis on reducing memory usage and improving source code readability and structure. As part of this effort, the shared memory data structure of Corsair is replaced with a distributed model. Domain decomposition of individual grids in the radial direction is also incorporated into Corsair for additional parallelization, along with a utility to automate this process in an optimal manner based on user input. This additional parallelization helps offset the inability to use the fine grain mp-threads parallelization in the original code on non-distributed memory architectures such as the PC Beowulf cluster used for this research. Conversion routines and utilities are created to handle differences in grid formats between Corsair and the FSI module. The resulting aeroelastic solver is tested using two simplified configurations. First, the well understood case of a flexible cylinder in cross flow is studied with the natural frequency of the cylinder set to the shedding frequency of the Von Karman streets. The cylinder is self excited and thus demonstrates the correct exchange of energy between the fluid and structural models. The second test case is based on the fourth standard configuration and demonstrates the ability of the solver to predict the dominant vibrational modes of an aeroelastic turbomachinery blade. For this case, a single blade from the fourth standard configuration is subjected to a step function from zero loading to the converged flow solution loading in order to excite the structural modes of the blade. These modes are then compared to those obtained from an in vacuo Ansys® analysis with good agreement between the two

Fundamental Approaches to Software Engineering

This open access book constitutes the proceedings of the 25th International Conference on Fundamental Approaches to Software Engineering, FASE 2022, which was held during April 4-5, 2022, in Munich, Germany, as part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2022. The 17 regular papers presented in this volume were carefully reviewed and selected from 64 submissions. The proceedings also contain 3 contributions from the Test-Comp Competition. The papers deal with the foundations on which software engineering is built, including topics like software engineering as an engineering discipline, requirements engineering, software architectures, software quality, model-driven development, software processes, software evolution, AI-based software engineering, and the specification, design, and implementation of particular classes of systems, such as (self-)adaptive, collaborative, AI, embedded, distributed, mobile, pervasive, cyber-physical, or service-oriented applications

Theoretical considerations and supporting evidence for the primary role of source geometry on field potential amplitude and spatial extent

Field potential (FP) recording is an accessible means to capture the shifts in the activity of neuron populations. However, the spatial and composite nature of these signals has largely been ignored, at least until it became technically possible to separate activities from co-activated sources in different structures or those that overlap in a volume. The pathway-specificity of mesoscopic sources has provided an anatomical reference that facilitates transcending from theoretical analysis to the exploration of real brain structures. We review computational and experimental findings that indicate how prioritizing the spatial geometry and density of sources, as opposed to the distance to the recording site, better defines the amplitudes and spatial reach of FPs. The role of geometry is enhanced by considering that zones of the active populations that act as sources or sinks of current may arrange differently with respect to each other, and have different geometry and densities. Thus, observations that seem counterintuitive in the scheme of distance-based logic alone can now be explained. For example, geometric factors explain why some structures produce FPs and others do not, why different FP motifs generated in the same structure extend far while others remain local, why factors like the size of an active population or the strong synchronicity of its neurons may fail to affect FPs, or why the rate of FP decay varies in different directions. These considerations are exemplified in large structures like the cortex and hippocampus, in which the role of geometrical elements and regional activation in shaping well-known FP oscillations generally go unnoticed. Discovering the geometry of the sources in play will decrease the risk of population or pathway misassignments based solely on the FP amplitude or temporal pattern

Fundamental Approaches to Software Engineering

This open access book constitutes the proceedings of the 25th International Conference on Fundamental Approaches to Software Engineering, FASE 2022, which was held during April 4-5, 2022, in Munich, Germany, as part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2022. The 17 regular papers presented in this volume were carefully reviewed and selected from 64 submissions. The proceedings also contain 3 contributions from the Test-Comp Competition. The papers deal with the foundations on which software engineering is built, including topics like software engineering as an engineering discipline, requirements engineering, software architectures, software quality, model-driven development, software processes, software evolution, AI-based software engineering, and the specification, design, and implementation of particular classes of systems, such as (self-)adaptive, collaborative, AI, embedded, distributed, mobile, pervasive, cyber-physical, or service-oriented applications

The Nature of Emission-Line Galaxies in Hierarchical Cosmologies

We use a galaxy formation model to study the nature and evolution of emission line galaxies. In particular, we focus on the properties of Ly-alpha and H-alpha emitters, due to their many cosmological applications being considered for current and future observational studies. By combining a semianalytical model with a large N-body simulation we predict the clustering of Ly-alpha emitters. With increasing redshift, Ly-alpha emitters are found to trace progressively rarer, higher density regions of the Universe. We measure the clustering of Ly-alpha emitters by constructing mock catalogues of surveys finding a good agreement between the model and the observational measurements. Furthermore, we use the mock catalogues to study the sample variance of current and forthcoming Ly-alpha surveys. Current surveys should be extended significantly in solid angle to allow a robust measurement of the clustering of Ly-alpha emitters, particularly at z>8. On the other hand, future space-based galaxy surveys will map the galaxy distribution using H-alpha emitters or H-band selected galaxies at 0.5<z<2 to constrain the nature of the dark energy by measuring the large-scale structure of the Universe. Therefore, we investigate the abundance and clustering of galaxies found using these two selections. H-alpha emitters are found to avoid massive dark matter haloes, whereas H-band selected galaxies are found in the highest mass haloes. By using mock catalogues, we predict the effectiveness of measuring the large scale structure of the Universe for a range of survey configurations using both galaxy selections. Finally, we study the escape of Ly-alpha photons from galaxies using a Monte Carlo radiative transfer code. We simulate galactic outflows in a semianalytical model to study the physical properties of Ly-alpha emitters in a cosmological context. We find that the escape fraction of Ly-alpha emitters can vary greatly depending on the properties of the galaxies, although our results depend on the outflow model used. Our results suggest the need to consider additional physical effects to understand the observed properties of Ly-alpha emitters

RFID Technology in Intelligent Tracking Systems in Construction Waste Logistics Using Optimisation Techniques

Construction waste disposal is an urgent issue for protecting our environment. This paper proposes a waste management system and illustrates the work process using plasterboard waste as an example, which creates a hazardous gas when land filled with household waste, and for which the recycling rate is less than 10% in the UK. The proposed system integrates RFID technology, Rule-Based Reasoning, Ant Colony optimization and knowledge technology for auditing and tracking plasterboard waste, guiding the operation staff, arranging vehicles, schedule planning, and also provides evidence to verify its disposal. It h relies on RFID equipment for collecting logistical data and uses digital imaging equipment to give further evidence; the reasoning core in the third layer is responsible for generating schedules and route plans and guidance, and the last layer delivers the result to inform users. The paper firstly introduces the current plasterboard disposal situation and addresses the logistical problem that is now the main barrier to a higher recycling rate, followed by discussion of the proposed system in terms of both system level structure and process structure. And finally, an example scenario will be given to illustrate the system’s utilization