Hardware accelerated authentication system for dynamic time-critical networks

The secure and efficient operation of time-critical networks, such as vehicular networks, smart-grid and other smart-infrastructures, is of primary importance in today’s society. It is crucial to minimize the impact of security mechanisms over such networks so that the safe and reliable operations of time-critical systems are not being interfered. Even though there are several security mechanisms, their application to smart-infrastructure and Internet of Things (IoT) deployments may not meet the ubiquitous and time-sensitive needs of these systems. That is, existing security mechanisms either introduce a significant computation and communication overhead, or they are not scalable for a large number of IoT components. In particular, as a primary authentication mechanism, existing digital signatures cannot meet the real-time processing requirements of time-critical networks, and also do not fully benefit from advancements in the underlying hardware/software of IoTs. As a part of this thesis, we create a reliable and scalable authentication system to ensure secure and reliable operation of dynamic time-critical networks like vehicular networks through hardware acceleration. The system is implemented on System-On-Chips (SoC) leveraging the parallel processing capabilities of the embedded Graphical Processing Units (GPUs) along with the CPUs (Central Processing Units). We identify a set of cryptographic authentication mechanisms, which consist of operations that are highly parallelizable while still maintain high standards of security and are also secure against various malicious adversaries. We also focus on creating a fully functional prototype of the system which we call a “Dynamic Scheduler” which will take care of scheduling the messages for signing or verification on the basis of their priority level and the number of messages currently in the system, so as to derive maximum throughput or minimum latency from the system, whatever the requirement may be

Algorithms and Software for High-Performance Fracture Simulation on GPU Architectures

Computer simulation of fracture in materials with nonlinear mechanical response can be computationally expensive. These simulations often require a large number of degrees of freedom, and the nonlinearity in the problem can pose difficulties when computing solutions. This work focuses on two material models. The first model consists of rigid bricks interacting through nonlinear cohesive springs. Fracture in the material occurs through the rupture of the cohesive springs. The second, more complicated, model consists of deformable elements interacting through nonlinear cohesive springs. In the first model, we assume the bricks are under a quasi-static loading scenario. With this assumption, the problem can be solved using a global Monte Carlo minimization algorithm to minimize the energy of the system. The energy in the system comes from the deformation and rupture of the nonlinear cohesive springs. Since these simulations have a high computational cost, we have developed a GPU-based (Graphics Processing Unit) Monte Carlo minimization algorithm that offers a significant speedup compared to a conventional multithreaded CPU-based algorithm. With the second model, we have dynamic simulations with explicit time discretization. In this case we compute the force, acceleration, velocity, and position explicitly. The force in the system comes from both the deformation of the elements as well as the deformation of the nonlinear cohesive springs. We have developed explicit, CPU-based methods and implicit-explict methods on both CPUs and GPUs. Our implicit-explict GPU-based method achieves substantial performance improvement compared to the explicit, CPU-based method. We present our GPU-based implementation of AES (Advanced Encryption Standard), which is used in the Monte Carlo minimization algorithm to generate random numbers. Our implementation is substantially faster than CPU-based implementation of AES. It is also faster than previous GPU implementations of AES

Comparison of implementations of cryptographic algorithms on the CPU and GPU

The aim of this Master's Thesis was to compare the serial implementations of block ciphers that run on CPU with corresponding parallel implementations that run on GPU. By analyzing the five finalists of the AES competition (Rijndael, Serpent, Twofish, MARS and RC6) we searched for possible improvements in their parallel implementations. Using the data parallelism techniques we implemented the algorithms in parallel and achieved the speed that was 20 times higher in comparison to the underlying serial implementations. We have also compared two different platforms for writing parallel programs on GPU: CUDA and OpenCL. In addition we implemented the bitslice implementations of algorithms Rijndael and Serpent for CUDA platform and compared them to data parallelism based implementations

メモリ帯域の高効率利用に基づくFPGAアクセラレータの設計に関する研究

Tohoku University亀山充隆課

Low-Overhead Techniques For Secure And Reliable Gpu Computing

In recent years, Graphics Processing Units (GPUs) have become a de facto choice to accelerate the computations in various domains such as machine learning, security, financial and scientific computing. GPUs leverage the inherent data parallelism in the target applications to provide high throughput at superior energy efficiency. Due to the rising usage of GPUs for a large number of applications, they are facing new challenges, especially in the security and reliability domains. From the security side, recently several microarchitectural attacks targeting GPUs have been demonstrated. These attacks leak the secret information stored on GPUs, for example, the parameters of a neural network (NN) model and the private user information. From the reliability side, the innovations to improve GPU memory systems are making them more susceptible to errors. My dissertation research focuses on addressing these security and reliability challenges in GPUs while minimizing the associated overhead of the proposed protection mechanisms. To improve GPU security, we focus on the previously demonstrated correlation timing attack. Such an attack exploits the deterministic nature of the coalescing mechanism in GPUs to correlate the execution time and the number of accesses. Consequently, an attacker can recover the encryption keys stored on GPUs. Therefore, to counter the correlation timing attack, we first introduce a randomized coalescing defense scheme (RCoal). RCoal randomizes the coalescing logic such that the attacker fails to correlate the execution time and the number of accesses. As a result, RCoal thwarts the correlation timing attack. Next, we propose a bucketing-based coalescing defense scheme, BCoal, which minimizes the variation in the number of memory accesses by generating a predetermined number (called buckets) of memory accesses. With low variation in the number of memory accesses, the attacker cannot correlate the application execution time and the secret information, thus failing the correlation timing attack. BCoal generates less memory traffic than RCoal and, therefore, is performance efficient. To improve GPU reliability, we address the data memory faults in GPU caches and DRAM. Existing reliability mechanisms of redundancy and check-pointing fail to scale with the increasing memory/computational demands on GPUs and quickly become impractical. To address this problem, we study a wide range of applications to nd that a very small fraction of the data memory is most vulnerable to faults. This small fraction of the data is not only highly accessed but also highly shared across GPU threads. Consequently, we propose and develop two reliability schemes to detect-only and to detect/correct faults in this most vulnerable data while incurring low overhead. The focus of ongoing and future work is to improve the reliability of machine learning applications

Implementación del algoritmo de cifrado AES mediante GPUS de Bajo Coste

El presente Trabajo Fin de Grado consiste en la implementación del algoritmo de encriptado Advanced Encryption Standard (AES), que también se conoce como Rijndael para 128 bits. De este modo, se puede acercar así al mundo de la encriptación a cualquier persona, ya que estas técnicas están cada día más presentes en nuestras vidas. AES es un algoritmo simétrico y aunque se ha demostrado que no es inmune frente a todos los ataques, si es altamente seguro si no se conoce su correspondiente clave de cifrado. Este algoritmo realiza múltiples operaciones sobre el estado a codificar, aunque son muy repetitivas. Lo que implica que para su ejecución se debe tener una gran capacidad de cálculo, así que se debe intentar reducir el tiempo de ejecución lo máximo posible ya que este hecho puede ralentizar en exceso la ejecución del algoritmo. En este trabajo, el algoritmo se implementa de dos modos diferentes. Primero utilizando la potencia del ordenador (CPU) y un lenguaje tradicional de programación como es el caso del lenguaje C. Más tarde se utiliza la potencia de la tarjeta gráfica del ordenador (GPU) y el lenguaje C con extensiones CUDA, paralelizando así el proceso. De esta manera se busca reducir el tiempo de ejecución del proceso A su vez también se analiza brevemente la historia de la encriptación y sus hitos más importantes, haciendo especial hincapié en la aparición del AES. Del mismo modo se estudia el funcionamiento y partes del AES tanto para codificar como para descodificar.This Bachellor Thesis consists on the implementation of the encryption algorithm Advanced Encryption Standard (AES), which is also know as Rijndael for 128 bits. In this way, it can be brought the world of encryption to anyone, because these techniques are ever more present in our lives. AES is a symmetric algorithm and although it has been shown that it is not immune to all atacks, if it is highly safe if the encryption key is unknow. This algorithm makes multiple operations on the encode state, although they are very repetitive. This implies, that for the implementation, we must have a big computational power, so we should try to reduce the execution time as much as posible as it can slow excessively execution of the algorithm. In this work, the algorithm is implemented in two different ways. First using the power of the computer (CPU) and C programming language. Later using the power of computer graphics card (GPU) and CUDA C language to parallelize the process. In this way, we want to reduce the execution time of the process. At the same, this Bachellor Thesis also discusses the history of encryption and its major events, with special emphasis on the appearance of AES. In the same way, the operation and parts of AES are studied for encryption and decryption.Ingeniería en Tecnologías Industriale

Information technologies: science, engineering, technology, education, health. Part 2

Подано тези доповідей науково-практичної конференції MicroCAD-2020 за теоретичними та практичними результатами наукових досліджень і розробок, які виконані викладачами вищої школи, науковими співробітниками, аспірантами, студентами, фахівцями різних організацій і підприємств. Для викладачів, наукових працівників, аспірантів, студентів, фахівців