A 16 channel high-voltage driver with 14 bit resolution for driving piezoelectric actuators

A high-voltage, 16 channel driver with a maximum voltage of 72 volt and 14 bit resolution in a high-voltage CMOS (HV-CMOS) process is presented. This design incorporates a 14 bit monotonic by design DAC together with a high-voltage complementary class AB output stage for each channel. All 16 channels are used for driving a piezoelectric actuator within the control loop of a micropositioning system. Since the output voltages are static most of the time, a class AB amplifier is used, implementing voltage feedback to achieve 14 bit accuracy. The output driver consists of a push-pull stage with a built-in output current limitation and high-impedance mode. Also a protection circuit is added which limits the internal current when the output voltage saturates against the high-voltage rail. The 14 bit resolution of each channel is generated with a segmented resistor string DAC which assures monotonic by design behavior by using leapfrogging of the buffers used between segments. A diagonal shuffle layout is used for the resistor strings leading to cancellation of first order process gradients. The dense integration of 16 channels with high peak currents results in crosstalk, countered in this design by using staggered switching and resampling of the output voltages

Development of an ARGOS beacon for the VORSat Cubesat

Tese de Mestrado Integrado. Engenharia Electrotécnica e de Computadores. Universidade do Porto. Faculdade de Engenharia. 201

The Design and Implementation of the Dynamic Ionosphere Cubesat Experiment (Dice) Science Instruments

Dynamic Ionosphere Cubesat Experiment (DICE) is a satellite project funded by the National Science Foundation (NSF) to study the ionosphere, more particularly Storm Enhanced Densities (SED) with a payload consisting of plasma diagnostic instrumentation. Three instruments onboard DICE include an Electric Field Probe (EFP), Ion Langmuir Probe (ILP), and Three Axis Magnetometer (TAM). The EFP measures electric fields from 8V and consists of three channels a DC to 40Hz channel, a Floating Potential Probe (FPP), and an spectrographic channel with four bands from 16Hz to 512Hz. The ILP measures plasma densities from 1x104 cm-3 to 2x107 cm-3. The TAM measures magnetic field strength with a range 0.5 Gauss with a sensitivity of 2nT. To achieve desired mission requirements careful selection of instrument requirements and planning of the instrumentation design to achieve mission success. The analog design of each instrument is described in addition to the digital framework required to sample the science data at a 70Hz rate and prepare the data for the Command and Data Handing (C&DH) system. Calibration results are also presented and show fulfillment of the mission and instrumentation requirements

Hardware design of a portable medical device to measure the quadriceps muscle group after a total knee arthroplasty by EMG, LBIA and clinical score methods

El propòsit d'aquest projecte és el disseny del hardware d'un dispositiu mèdic portàtil per a mesurar senyals d'electromiografia (EMG) i bioimpedància localitzada (LBIA), que s'utilitzarà per avaluar la progressió de dues pròtesis de genoll (Medial-Pivot i Ultra- Congruent) en pacients operats d'una artroplàstia total de genoll per a l'hospital Germans Trias i Pujol de Badalona. Per això, s'ha realitzat un estudi complet sobre els senyals d'EMG i LBIA, per tal de definir les característiques necessàries de l'equip mèdic i poder optimitzar el disseny electrònic. Per l'adquisició de senyals EMG, s'ha dissenyat i simulat un sistema compost per diferents fases, que treballen independentment per adquirir, amplificar, filtrar i adaptar el senyal EMG pel seu futur processament digital. D'altra banda, per obtenir valors de la bioimpedància localitzada dels diferents músculs que conformen el quàdriceps, s'ha dissenyat un sistema compost per dos grans blocs; el primer bloc és l'etapa d'injecció, on es genera i s'injecta un senyal feble de corrent altern a la zona a mesurar, mentre que el segon bloc, és l'etapa d'adquisició de senyals. Aquest últim s'encarrega d'adquirir la diferència de voltatge produïda per la injecció de corrent al múscul (anteriorment mencionat) per després calcular la bioimpedància a partir de la llei d'ohm. Tots els senyals són digitalitzats mitjançant el microcontrolador STM32F407VG, que s'encarregarà de processar i aconseguir les dades claus per determinar quina de les deus pròtesis desenvolupa una millor funció mecànica i una millor adaptació biològica. És important remarcar que tot el disseny, sigui per a EMG o LBIA s'ha dut a terme de manera discreta sense fer servir Front-Ends comercials o integrats complexos més que l'amplificador d'instrumentació o ADC. En addició, el present treball inclou una primera estimació dels costos de producció i fabricació per a una sola unitat, càlculs de consums i funcionament (sorolls, CMRR del sistema i amplada de banda) i una simulació completa d'EMG i LBIA per observar com funciona i es du a terme cada etapa del circuit. Finalment, en tractar-se d'un equip mèdic, també s'ha revisat la normativa aplicable i se n'ha analitzat l'impacte ambiental, s'ha proposat i definit diferents punts per a futurs treballs, com podria ser la validació i testatge de l'equip, càlculs més aproximats de consums i perfilar la bill of materials (BOM) per a grans demandes de components.The purpose of this project is the hardware design of a portable medical device to measure electromyography (EMG) and localized bioimpedance (LBIA) signals, which will be used to evaluate the adaptability and progression of two knee prostheses (medial-pivot and ultra-congruent) in patients undergoing total knee arthroplasty at the Germans Trias i Pujol Hospital in Badalona. For this, the present work undercovers the relevant properties of the EMG and LBIA signals in order to define the characteristics of the medical equipment and thus optimize its electronic design. For the EMG measurements, a system made up of different stages has been designed and simulated. These phases work independently to acquire, amplify, filter, and adapt the EMG signal for its further digital processing. On the other hand, to obtain the bioimpedance values of different quadriceps muscles, a system composed of two large blocks has been designed; the first is the injection block, where a weak alternating current signal is generated and injected into the area to be measured, while the second block is the signal acquisition stage. The purpose of the latter is to acquire the voltage difference produced by the injection of current (mentioned above) and then obtain the bioimpedance from Ohm's law. All the signals are digitized from the STM32F407VG microcontroller, which will be in charge of processing and obtaining the key data to determine which of the two prostheses performs a better mechanical function and biological adaptation. It is important to note that the entire design, whether for EMG or LBIA, has been developed discreetly without using commercial Front-Ends or complex ICs other than the instrumentation amplifier or ADC. In addition, the thesis includes a first estimation of the production and manufacturing costs for a single unit, calculations of consumption and work operation (noise, CMRR of the system and bandwidth) and a complete simulation of EMG and LBIA to observe how it works on each stage for both circuits. Finally, as it is a medical device, the applicable regulations have also been reviewed and its environmental impact has been analysed. Additionally, different points have been proposed and defined for future work, such as the construction of the PCB and its respective validation, improving both the consumption calculations and the list of materials (BOM) for large component demands.El propósito de este proyecto es el diseño del Hardware de un dispositivo médico portátil para mediciones de electromiografía (EMG) y bioimpedancia localizada (LBIA), que se utilizará para estudiar la evolución de la adaptabilidad y funcionamiento de dos prótesis de rodilla (medial-pívot y ultracongruente) en pacientes operados de artroplastia total de rodilla en el Hospital Germans Trias i Pujol de Badalona. Para ello, se ha realizado un estudio exhaustivo sobre las propiedades de las señales de EMG y LBIA con la finalidad de definir las características del equipo médico y de esta forma, optimizar el diseño electrónico del mismo. Para la lectura de mediciones EMG, se ha diseñado y simulado un sistema constituido por distintas etapas, que trabajan independientemente para adquirir, amplificar, filtrar, y adaptarla señal EMG para su posterior procesado digital. Por otro lado, para obtener los valores de bioimpedancia de distintos músculos del cuádriceps, se ha diseñado un sistema compuesto por dos grandes bloques; el primero es el bloque de inyección, donde se genera y se inyecta una señal débil de corriente alterna en la zona a medir, mientras que el segundo bloque es la etapa de adquisición de señales. Esta última tiene como finalidad adquirir la diferencia de voltaje producido por la inyección de corriente (anteriormente mencionada) para después obtener la bioimpedancia a partir de la ley de ohm. Todas las señales son digitalizadas a partir del microcontrolador STM32F407VG, que se encargará de procesar y obtener los datos claves para determinar cuál de las dos prótesis desempeña una mejor función mecánica y adaptación biológica. Es importante remarcar que todo el diseño, ya sea para EMG o LBIA, se ha desarrollado de manera discreta sin usar Front-Ends comerciales o integrados complejos más que el amplificador de instrumentación o ADC. En adición, la tesis incluye una primera estimación de los costes de producción y fabricación para una sola unidad, cálculos de consumos y funcionamiento (ruidos, CMRR del sistema y ancho de banda) y una simulación completa de EMG y LBIA para observar cómo funciona y se desarrolla cada etapa de los distintos circuitos. Finalmente, al tratarse de un equipo médico, también se ha revisado la normativa aplicable y se ha analizado el impacto ambiental del mismo. Por último, se han propuesto y definido distintos puntos para futuros trabajos, como es la construcción de la PCB y su respectiva validación, realizar cálculos más aproximados de consumos y perfilar la lista de materiales (BOM) para grandes demandas de componentes

Ultra-low Power Circuits for Internet of Things (IOT)

Miniaturized sensor nodes offer an unprecedented opportunity for the semiconductor industry which led to a rapid development of the application space: the Internet of Things (IoT). IoT is a global infrastructure that interconnects physical and virtual things which have the potential to dramatically improve people's daily lives. One of key aspect that makes IoT special is that the internet is expanding into places that has been ever reachable as device form factor continue to decreases. Extremely small sensors can be placed on plants, animals, humans, and geologic features, and connected to the Internet. Several challenges, however, exist that could possibly slow the development of IoT. In this thesis, several circuit techniques as well as system level optimizations to meet the challenging power/energy requirement for the IoT design space are described. First, a fully-integrated temperature sensor for battery-operated, ultra-low power microsystems is presented. Sensor operation is based on temperature independent/dependent current sources that are used with oscillators and counters to generate a digital temperature code. Second, an ultra-low power oscillator designed for wake-up timers in compact wireless sensors is presented. The proposed topology separates the continuous comparator from the oscillation path and activates it only for short period when it is required. As a result, both low power tracking and generation of precise wake-up signal is made possible. Third, an 8-bit sub-ranging SAR ADC for biomedical applications is discussed that takes an advantage of signal characteristics. ADC uses a moving window and stores the previous MSBs voltage value on a series capacitor to achieve energy saving compared to a conventional approach while maintaining its accuracy. Finally, an ultra-low power acoustic sensing and object recognition microsystem that uses frequency domain feature extraction and classification is presented. By introducing ultra-low 8-bit SAR-ADC with 50fF input capacitance, power consumption of the frontend amplifier has been reduced to single digit nW-level. Also, serialized discrete Fourier transform (DFT) feature extraction is proposed in a digital back-end, replacing a high-power/area-consuming conventional FFT.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137157/1/seojeong_1.pd

Linearization of Time-encoded ADCs Architectures for Smart MEMS Sensors in Low Power CMOS Technology

Mención Internacional en el título de doctorIn the last few years, the development of mobile technologies and machine learning applications has increased the demand of MEMS-based digital microphones. Mobile devices have several microphones enabling noise canceling, acoustic beamforming and speech recognition. With the development of machine learning applications the interest to integrate sensors with neural networks has increased. This has driven the interest to develop digital microphones in nanometer CMOS nodes where the microphone analog-front end and digital processing, potentially including neural networks, is integrated on the same chip. Traditionally, analog-to-digital converters (ADCs) in digital microphones have been implemented using high order Sigma-Delta modulators. The most common technique to implement these high order Sigma-Selta modulators is switchedcapacitor CMOS circuits. Recently, to reduce power consumption and make them more suitable for tasks that require always-on operation, such as keyword recognition, switched-capacitor circuits have been improved using inverter-based operational amplifier integrators. Alternatively, switched-capacitor based Sigma- Delta modulators have been replaced by continuous time Sigma-Delta converters. Nevertheless, in both implementations the input signal is voltage encoded across the modulator, making the integration in smaller CMOS nodes more challenging due to the reduced voltage supply. An alternative technique consists on encoding the input signal on time (or frequency) instead of voltage. This is what time-encoded converters do. Lately, time-encoding converters have gained popularity as they are more suitable to nanometer CMOS nodes than Sigma-Delta converters. Among the ones that have drawn more interest we find voltage-controlled oscillator based ADCs (VCOADCs). VCO-ADCs can be implemented using CMOS inverter based ring oscillators (RO) and digital circuitry. They also show noise-shaping properties. This makes them a very interesting alternative for implementation of ADCs in nanometer CMOS nodes. Nevertheless, two main circuit impairments are present in VCO-ADCs, and both come from the oscillator non-idealities. The first of them is the oscillator phase noise, that reduces the resolution of the ADC. The second is the non-linear tuning curve of the oscillator, that results in harmonic distortion at medium to high input amplitudes. In this thesis we analyze the use of time encoding ADCs for MEMS microphones with special focus on ring oscillator based ADCs (RO-ADCs). Firstly, we study the use of a dual-slope based SAR noise shaped quantizer (SAR-NSQ) in sigma-delta loops. This quantizer adds and extra level of noise-shaping to the modulator, improving the resolution. The quantizer is explained, and equations for the noise transfer function (NTF) of a third order sigma-delta using a second order filter and the NSQ are presented. Secondly, we move our attention to the topic of RO-ADCs. We present a high dynamic range MEMS microphone 130nm CMOS chip based on an open-loop VCO-ADC. This dissertation shows the implementation of the analog front-end that includes the oscillator and the MEMS interface, with a focus on achieving low power consumption with low noise and a high dynamic range. The digital circuitry is left to be explained by the coauthor of the chip in his dissertation. The chip achieves a 80dBA peak SNDR and 108dB dynamic range with a THD of 1.5% at 128 dBSPL with a power consumption of 438μW. After that, we analyze the use of a frequency-dependent-resistor (FDR) to implement an unsampled feedback loop around the oscillator. The objective is to reduce distortion. Additionally phase noise mitigation is achieved. A first topology including an operational amplifier to increase the loop gain is analyzed. The design is silicon proven in a 130 nm CMOS chip that achieves a 84 dBA peak SNDR with an analog power consumption of 600μW. A second topology without the operational amplifier is also analyzed. Two chips are designed with this topology. The first chip in 130 nm CMOS is a full VCO-ADC including the frequencyto- digital converter (F2D). This chip achieves a peak SNDR of 76.6 dBA with a power consumption of 482μW. The second chip includes only the oscillator and is implemented in 55nm CMOS. The peak SNDR is 78.15 dBA and the analog power consumption is 153μW. To finish this thesis, two circuits that use an FDR with a ring oscillator are presented. The first is a capacity-to-digital converter (CDC). The second is a filter made with an FDR and an oscillator intended for voice activity detection tasks (VAD).En los últimos años, el desarrollo de las tecnologías móviles y las aplicaciones de machine-learning han aumentado la demanda de micrófonos digitales basados en MEMS. Los dipositivos móviles tienen varios micrófonos que permiten la cancelación de ruido, el beamforming o conformación de haces y el reconocimiento de voz. Con el desarrollo de aplicaciones de aprendizaje automático, el interés por integrar sensores con redes neuronales ha aumentado. Esto ha impulsado el interés por desarrollar micrófonos digitales en nodos CMOS nanométricos donde el front-end analógico y el procesamiento digital del micrófono, que puede incluir redes neuronales, está integrado en el mismo chip. Tradicionalmente, los convertidores analógicos-digitales (ADC) en micrófonos digitales han sido implementados utilizando moduladores Sigma-Delta de orden elevado. La técnica más común para implementar estos moduladores Sigma- Delta es el uso de circuitos CMOS de capacidades conmutadas. Recientemente, para reducir el consumo de potencia y hacerlos más adecuados para las tareas que requieren una operación continua, como el reconocimiento de palabras clave, los convertidores Sigma-Delta de capacidades conmutadas has sido mejorados con el uso de integradores implementados con amplificadores operacionales basados en inversores CMOS. Alternativamente, los Sigma-Delta de capacidades conmutadas han sido reemplazados por moduladores en tiempo continuo. No obstante, en ambas implementaciones, la señal de entrada es codificada en voltaje durante el proceso de conversión, lo que hace que la integración en nodos CMOS más pequeños sea complicada debido a la menor tensión de alimentación. Una técnica alternativa consiste en codificar la señal de entrada en tiempo (o frecuencia) en lugar de tensión. Esto es lo que hacen los convertidores de codificación temporal. Recientemente, los convertidores de codificación temporal han ganado popularidad ya que son más adecuados para nodos CMOS nanométricos que los convertidores Sigma-Delta. Entre los que más interés han despertado encontramos los ADCs basados en osciladores controlados por tensión (VCO-ADC). Los VCO-ADC se pueden implementar usando osciladores en anillo (RO) implementados con inversores CMOS y circuitos digitales. Esta familia de convertidores también tiene conformado de ruido. Esto los convierte en una alternativa muy interesante para la implementación de convertidores en nodos CMOS nanométricos. Sin embargo, dos problemas principales están presentes en este tipo de ADCs debidos ambos a las no idealidades del oscilador. El primero de los problemas es la presencia de ruido de fase en el oscilador, lo que reduce la resolución del ADC. El segundo es la curva de conversion voltaje-frecuencia no lineal del oscilador, lo que causa distorsión a amplitudes medias y altas. En esta tesis analizamos el uso de ADCs de codificación temporal para micrófonos MEMS, con especial interés en ADCS basados en osciladores de anillo (RO-ADC). En primer lugar, estudiamos el uso de un cuantificador SAR con conformado de ruido (SAR-NSQ) en moduladores Sigma-Delta. Este cuantificador agrega un orden adicional de conformado de ruido al modulador, mejorando la resolución. En este documento se explica el cuantificador y obtienen las ecuaciones para la función de transferencia de ruido (NTF) de un sigma-delta de tercer orden usando un filtro de segundo orden y el NSQ. En segundo lugar, dirigimos nuestra atención al tema de los RO-ADC. Presentamos el chip de un micrófono MEMS de alto rango dinámico en CMOS de 130 nm basado en un VCO-ADC de bucle abierto. En esta tesis se explica la implementación del front-end analógico que incluye el oscilador y la interfaz con el MEMS. Esta implementación se ha llevado a cabo con el objetivo de lograr un bajo consumo de potencia, un bajo nivel de ruido y un alto rango dinámico. La descripción del back-end digital se deja para la tesis del couator del chip. La SNDR de pico del chip es de 80dBA y el rango dinámico de 108dB con una THD de 1,5% a 128 dBSPL y un consumo de potencia de 438μW. Finalmente, se analiza el uso de una resistencia dependiente de frecuencia (FDR) para implementar un bucle de realimentación no muestreado alrededor del oscilador. El objetivo es reducir la distorsión. Además, también se logra la mitigación del ruido de fase del oscilador. Se analyza una primera topologia de realimentación incluyendo un amplificador operacional para incrementar la ganancia de bucle. Este diseño se prueba en silicio en un chip CMOS de 130nm que logra un pico de SNDR de 84 dBA con un consumo de potencia de 600μW en la parte analógica. Seguidamente, se analiza una segunda topología sin el amplificador operacional. Se fabrican y miden dos chips diseñados con esta topologia. El primero de ellos en CMOS de 130 nm es un VCO-ADC completo que incluye el convertidor de frecuencia a digital (F2D). Este chip alcanza un pico SNDR de 76,6 dBA con un consumo de potencia de 482μW. El segundo incluye solo el oscilador y está implementado en CMOS de 55nm. El pico SNDR es 78.15 dBA y el el consumo de potencia analógica es de 153μW. Para cerrar esta tesis, se presentan dos circuitos que usan la FDR con un oscilador en anillo. El primero es un convertidor de capacidad a digital (CDC). El segundo es un filtro realizado con una FDR y un oscilador, enfocado a tareas de detección de voz (VAD).Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Antonio Jesús Torralba Silgado.- Secretaria: María Luisa López Vallejo.- Vocal: Pieter Rombout

A Monolithic Gm-C Filter based Very Low Power, Programmable, and Multi-Channel Harmonic Discrimination System using Analog Signal Processing

A highly selective monolithic band-pass filter with programmable characteristics at micro-power operation is presented. Very low power signal processing is of great interest in wireless sensing and Internet-of-Things applications. This filter enables long-term battery powered operation of a highly selective harmonic signal discriminator for an analog signal processing system. The Gm-C biquadratic circuits were fabricated in a 0.18-μm [micrometer] CMOS process. Each 2nd-order biquad filter nominally consumes 20 μW [microwatt] and can be programmed for the desired gain (0db3dB), quality factor (5 to 20), and center-frequency from 1kHz to 100kHz. The 8th-order filter channel achieved an effective quality factor of 30 at 100kHz with an overall power consumption of 108 μW

3중 샘플링 방식 델타-시그마 ADC를 이용한 디지털 Capacitive MEMS 마이크로폰

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 김수환.본 논문에서는 트리플 샘플링 적분기를 사용한 Capacitive 방식의 MEMS 마이크로폰이 제시되었다. 트리플 샘플링은 델타-시그마 방식의 아날로그-디지털 변환기의 첫 번째 적분기에 사용되었고 크게 두 가지의 동작으로 구분된다. 첫 번째로 적분기의 입력에서 반주기 지연 차동 입력을 빼서 신호 크기를 2배로 만들는 방식. 두 번째로 DAC의 피드백 커패시터를 샘플링 커패시터로 사용하여 입력 전압을 추가로 증가시키는 방식이다. 추가적으로 기존에서 샘플링 커패시터를 증가시켜 신호의 크기를 증폭시키는 방식과 결합하여 실수배의 이득을 얻을 수 있다. 또한 추가적인 커패시터, 타이밍, 전류 소모 없이 구조 변경만으로 이를 달성하였기 때문에 별다른 trade-off 없이 신호의 크기를 증폭시킬 수 있었다. 추가적으로 트리플 샘플링 방식의 적분기 신호 전달 함수 및 잡음 분석 또한 포함하였다. 우리의 readout 회로는 공급 전압이 1.8V인 0.18 m CMOS 공정으로 구현하였고 single-ended capacitive MEMS 트랜스듀서를 사용하여 측정하였다. 전류 소모량은 520 μA 이다. 마이크로폰은 A-weighted 신호 대 잡음 비는 62.1 dBA, 음향 과부하 지점은 115 dB SPL을 달성하였고 칩의 die size는 0.98〖"mm" 〗^2 이다.A triple-sampling ΔΣ ADC can replace the programmable-gain amplifier commonly used in the readout circuit for a digital capacitive MEMS microphone. The input voltage can then be multiplied by subtracting a further half-period delayed differential input and using the feedback capacitor of the DAC as a sampling capacitor. This triple-sampling technique results in a readout circuit with sensitivity and noise performance comparable to recent designs, but with a reduced power requirement. CMRR improvement is achieved by subtracting differential inputs and superior noise performance compare to conventional structure, as amplifier noise and DAC kT/C noise is not amplified by triple-sampling structure while the signal is increased by its gain. Triple-sampling also can be operated as a single-to-differential circuit. A MEMS microphone incorporating this readout circuit, fabricated in a 0.18μm CMOS process, achieved an A-weighted SNR of 62.1 dBA at 94 dB SPL with 520 μA current consumption, to which triple-sampling was shown to contribute 4.5 dBA.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.1.1 MEMS MICROPHONE TRENDS 1 1.1.2 TYPE OF MEMS MICROPHONES 4 1.1.3 PREVIOUS WORKS 7 1.2 MEMS MICROPHONE BASIC TERMS 9 1.3 THESIS ORGANIZATION 12 CHAPTER 2 SYSTEM OVERVIEW 13 2.1 SYSTEM ARCHITECTURE 13 CHAPTER 3 INTERFACE CIRCUITS AND POWER MANAGEMENT CIRCUITS 16 3.1 PSEUDO-DIFFERENTIAL SOURCE FOLLOWER 17 3.2 CHARGE PUMP 19 3.3 LOW DROPOUT REGULATOR 22 3.3.1 DESIGN CONSIDERATION OF LOW DROPOUT REGULATOR 22 3.3.2 IMPLEMENTATION OF LOW DROPOUT REGULATOR 26 CHAPTER 4 TRIPLE-SAMPLING DELTA-SIGMA ADC 31 4.1 BASIC OF DELTA-SIGMA ADC 31 4.2 IMPLEMENTATION OF TRIPLE-SAMPLING DELTA-SIGMA MODULATOR 37 4.2.1 CONVENTIONAL 1ST INTEGRATOR STRUCTURE 37 4.2.2 CROSS-SAMPLING 1ST INTEGRATOR 40 4.2.3 TRIPLE-SAMPLING 1ST INTEGRATOR 43 4.2.4 STF ANALYSIS OF TRIPLE-SAMPLING 1ST INTEGRATOR 47 4.2.5 THERMAL NOISE ANALYSIS OF TRIPLE-SAMPLING 1ST INTEGRATOR 51 4.2 CIRCUIT IMPLEMENTATION OF DELTA-SIGMA ADC 57 CHAPTER 5 MEASUREMENT RESULTS 64 5.1 MEASUREMENT ENVIRONMENT 64 5.2 MEASUREMENT RESULTS 67 5.3 PERFORMANCE SUMMARY 72 CHAPTER 6 CONCLUSION 74 BIBLIOGRAPHY 76 한글초록 79박