Single-MOSFET DC thermal sensor for RF-amplifier central frequency extraction

© 2017 Elsevier B.V. A DC thermal sensor based on a single metal-oxide-semiconductor field-effect transistor (MOSFET) is proposed to extract high-frequency electrical features of embedded circuits. The MOSFET sensor is monolithically integrated with the circuit under test (CUT) and then monitors by thermal means the DC power dissipated by the CUT, which carries high-frequency electrical information. After explaining the theory behind this testing approach, the paper demonstrates the feasibility of the proposed MOSFET sensor through simulations and experiments. These are carried out using a radio-frequency (RF) power amplifier as a CUT and thermally extracting its central frequency (440 MHz). The MOSFET sensor results are assessed using an infrared camera as a reference. The main advantage of the proposed sensing method is that the impact on the integrated circuit (IC) layout area is minimum, which is crucial when testing RF-ICs. Moreover, in comparison with previous works, the cost and complexity of the required instrumentation is lower.Postprint (author's final draft

MOSFET dynamic thermal sensor for IC testing applications

This paper analyses how a single metal-oxide-semiconductor field-effect transistor (MOSFET) can be employed as a thermal sensor to measure on-chip dynamic thermal signals caused by a power-dissipating circuit under test (CUT). The measurement is subjected to two low-pass filters (LPF). The first LPF depends on the thermal properties of the heat-conduction medium (i.e. silicon) and the CUT-sensor distance, whereas the second depends on the electrical properties of the sensing circuit such as the bias current and the dimensions of the MOSFET sensor. This is evaluated along the paper through theoretical models, simulations, and experimental data resulting from a chip fabricated in 0.35 mu m CMOS technology. Finally, the proposed thermal sensor and the knowledge extracted from this paper are applied to estimate the linearity of a radio-frequency (RF) amplifier. (C) 2016 Elsevier B.V. All rights reserved.Peer ReviewedPostprint (author's final draft

Output Power and Gain Monitoring in RF CMOS Class A Power Amplifiers by Thermal Imaging

© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The viability of using off-chip single-shot imaging techniques for local thermal testing in integrated Radio Frequency (RF) power amplifiers (PA’s) is analyzed. With this approach, the frequency response of the output power and power gain of a Class A RF PA is measured, also deriving information about the intrinsic operation of its transistors. To carry out this case study, the PA is heterodynally driven, and its electrical behavior is down converted into a lower frequency thermal field acquirable with an InfraRed Lock-In Thermography (IR-LIT) system. After discussing the theory, the feasibility of the proposed approach is demonstrated and assessed with thermal sensors monolithically integrated in the PA. As crucial advantages to RF-testing, this local approach is noninvasive and demands less complex instrumentation than the mainstream commercially available solutions.Peer ReviewedPostprint (author's final draft

CIRCUIT MODULES FOR BROADBAND CMOS SIX-PORT SYSTEMS

This dissertation investigates four circuit modules used in a CMOS integrated six-port measurement system. The first circuit module is a wideband power source generator, which can be implemented with a voltage controlled ring oscillator. The second circuit module is a low-power 0.5 GHz - 20.5 GHz power detector with an embedded amplifier and a wideband quasi T-coil matching network. The third circuit module is a six-port circuit, which can be implemented with distributed or lumped- lement techniques. The fourth circuit module is the phase sifter used as calibration loads. The theoretical analysis, circuit design, simulated or experimental verifications of each circuit module are also included

A Self-Calibrated Power Detector and Current Sensor for Use in a Power Amplifier Control Circuit

The power amplifier in a transmitter, especially high-power transmitters, generally uses more power than any other component in the signal chain. As a result, large power savings can be achieved if the efficiency of the power amplifier is optimized. Additionally, power amplifiers in high-power transmitters generally experience substantial amounts of reliability-reducing stress such as high temperature operation. Given these considerations, a power amplifier control loop is proposed which will calculate various parameters of the amplifier, such as the power-added efficiency. This control loop will then adjust the input power and DC bias current of the power amplifier to maximize the efficiency while also ensuing the amplifier is not placed in a situation where its reliability is compromised. This thesis will discuss the design of two major blocks that are required in this control loop: a DC bias current sensor and a power detector. The DC bias current sensor must accurately measure the DC bias of the power amplifier since this current is used to calculate the DC power dissipation for the power-added efficiency. In order to ensure the DC current sensor’s output is accurate over a wide temperature range, a reference current calibration scheme is introduced. The fabricated current sensor is able to achieve a measurement accuracy of +/-1% over a current range from 100mA to 4A. The power detector must measure the input and output power of the power amplifier since the power added efficiency takes into account the gain of the amplifier. The proposed power detector utilizes an on-chip reference generator in order to calibrate the peak detector used and provide an accurate and absolute power level. The simulated power detector is able to provide an accuracy of +/-0.5dB over a dynamic range of 40dB. These two designs will be incorporated in the overall power amplifier control system in future work

Design of a CMOS power amplifier and built-in sensors for variability monitoring and compensation

This research thesis aims to develop a system composed by a a CMOS power amplifier and built-in sensors for variability monitoring and compensation. The integration of monitoring systems with high frequency analog circuits is commonly used for performance optimization and control. In addition, built-in sensors are used in quality testing, improving the yield by detecting circuit faults during the fabrication of these. Typically, most of the built-in sensors are electrically connected to a node of the circuit under test, affecting its performance. In tuned power amplifers, for instance, a small load variation can cause a degradation of its output power and effciency. Hence, the integration between the circuit under test and the monitoring block should be carefully designed. These loading effects can be avoided using non-invasive solutions such as temperature sensors. An integrated circuit composed by a CMOS power amplifer, two amplitude detectors and a temperature sensor is implemented in this work. The degradation of the power amplifier performance due to variability effects is accelerated by increasing its supply voltage. A feedback loop is added to control and adjust the system operation, stress the amplifier and accelerate its degradation, monitor the amplifier performance using the sensors and compensate the observed degradation. The design of each one of the main parts of the system is presented through this work, explaining their theoretical basis and validating their operation with simulations results. Finally, all the parts are integrated together, and a feedback loop with a control algorithm is proposed to monitor and compensate the DUT variability effects

Ultra Low Power IEEE 802.15.4/ZIGBEE Compliant Transceiver

Low power wireless communications is the most demanding request among all wireless users. A battery life that can survive for years without being replaced, makes it realistic to implement many applications where the battery is unreachable (e.g. concrete walls) or expensive to change (e.g underground applications). IEEE 802.15.4/ZIGBEE standard is published to cover low power low cost applications, where the battery life can last for years, because of the 1% duty cycle of operation. A fully integrated 2.4GHz IEEE802.15.4 Compliant transceiver suitable for low power, low cost ZIGBEE applications is implemented. Direct conversion architecture is used in both Receiver and Transmitter, to achieve the minimum possible power and area. The chip is fabricated in a standard 0.18um CMOS technology. In the transmit mode, the transmitter chain (Modulator to PA) consumes 25mW, while in the receive mode, the iv receiver chain (LNA to Demodulator) consumes 5mW. The Integer-N Frequency Synthesizer consumes 8.5mW. Other Low power circuits are reported; A 13.56 Passive RFID tag and a low power ADC suitable for Built-In-Testing applications

Conception et réalisation de fonctions millimétriques en technologie BiCMOS 55nm

In the past few years, the feasibility of high performance millimeter-wave(mmWave) fully-integrated transceivers has been widely demonstrated in both CMOS andBiCMOS silicon technologies. Nowadays, automatic level control (ALC) solutions and in-situtesting (BIT: Built in Testing) and characterization of mmWave components, constitute themajor research interest in mmWave domain. This work focus on the development of the mainbuilding blocks (power detectors and baluns) that meet the requirement of the today’smmWave ALC and BIT applications. The developed prototypes take advantage of the highperformances transistors offered by the BiCMOS 55 nm technology, from STMicroelectronics, aswell as the high performances of the slow-wave based passive components developed by theIMEP-LAHC laboratory. Several prototypes were developed as a proof of concept for thedesignated applications. This work helps future generation millimeter-wave systems to havefaster development and better robustness.Au cours des dernières années, la faisabilité des émetteurs-récepteurs millimétriques entièrement intégrés a été largement démontrée en technologies silicium CMOS et BiCMOS. Deux axes sont actuellement très porteurs dans ce domaine : (1) l’amélioration des performances à travers des boucles d’asservissement intégrées (ALC : Automatique Level Control), (2) le développement de solutions de caractérisation sur silicium des composants millimétriques (BIT : Built In Test). L’objectif principal de cette thèse est de développer les blocsde base (détecteurs de puissance et baluns) pour répondre aux besoins actuels des applications ALC et BIT. Les circuits réalisés combinent l’avantage de composants actifs de la technologie BiCMOS 55 nm, de STMicroelectronics, avec l’avantage des structures passives à ondes lentes développées à l’IMEP-LAHC. Ce travail permet un développement plus rapide et robuste pour la future génération de systèmes millimétriques

Conception et réalisation de fonctions millimétriques en technologie BiCMOS 55nm

In the past few years, the feasibility of high performance millimeter-wave(mmWave) fully-integrated transceivers has been widely demonstrated in both CMOS andBiCMOS silicon technologies. Nowadays, automatic level control (ALC) solutions and in-situtesting (BIT: Built in Testing) and characterization of mmWave components, constitute themajor research interest in mmWave domain. This work focus on the development of the mainbuilding blocks (power detectors and baluns) that meet the requirement of the today’smmWave ALC and BIT applications. The developed prototypes take advantage of the highperformances transistors offered by the BiCMOS 55 nm technology, from STMicroelectronics, aswell as the high performances of the slow-wave based passive components developed by theIMEP-LAHC laboratory. Several prototypes were developed as a proof of concept for thedesignated applications. This work helps future generation millimeter-wave systems to havefaster development and better robustness.Au cours des dernières années, la faisabilité des émetteurs-récepteurs millimétriques entièrement intégrés a été largement démontrée en technologies silicium CMOS et BiCMOS. Deux axes sont actuellement très porteurs dans ce domaine : (1) l’amélioration des performances à travers des boucles d’asservissement intégrées (ALC : Automatique Level Control), (2) le développement de solutions de caractérisation sur silicium des composants millimétriques (BIT : Built In Test). L’objectif principal de cette thèse est de développer les blocsde base (détecteurs de puissance et baluns) pour répondre aux besoins actuels des applications ALC et BIT. Les circuits réalisés combinent l’avantage de composants actifs de la technologie BiCMOS 55 nm, de STMicroelectronics, avec l’avantage des structures passives à ondes lentes développées à l’IMEP-LAHC. Ce travail permet un développement plus rapide et robuste pour la future génération de systèmes millimétriques

Development of Robust Analog and Mixed-Signal Circuits in the Presence of Process- Voltage-Temperature Variations

Continued improvements of transceiver systems-on-a-chip play a key role in the advancement of mobile telecommunication products as well as wireless systems in biomedical and remote sensing applications. This dissertation addresses the problems of escalating CMOS process variability and system complexity that diminish the reliability and testability of integrated systems, especially relating to the analog and mixed-signal blocks. The proposed design techniques and circuit-level attributes are aligned with current built-in testing and self-calibration trends for integrated transceivers. In this work, the main focus is on enhancing the performances of analog and mixed-signal blocks with digitally adjustable elements as well as with automatic analog tuning circuits, which are experimentally applied to conventional blocks in the receiver path in order to demonstrate the concepts. The use of digitally controllable elements to compensate for variations is exemplified with two circuits. First, a distortion cancellation method for baseband operational transconductance amplifiers is proposed that enables a third-order intermodulation (IM3) improvement of up to 22dB. Fabricated in a 0.13µm CMOS process with 1.2V supply, a transconductance-capacitor lowpass filter with the linearized amplifiers has a measured IM3 below -70dB (with 0.2V peak-to-peak input signal) and 54.5dB dynamic range over its 195MHz bandwidth. The second circuit is a 3-bit two-step quantizer with adjustable reference levels, which was designed and fabricated in 0.18µm CMOS technology as part of a continuous-time SigmaDelta analog-to-digital converter system. With 5mV resolution at a 400MHz sampling frequency, the quantizer's static power dissipation is 24mW and its die area is 0.4mm^2. An alternative to electrical power detectors is introduced by outlining a strategy for built-in testing of analog circuits with on-chip temperature sensors. Comparisons of an amplifier's measurement results at 1GHz with the measured DC voltage output of an on-chip temperature sensor show that the amplifier's power dissipation can be monitored and its 1-dB compression point can be estimated with less than 1dB error. The sensor has a tunable sensitivity up to 200mV/mW, a power detection range measured up to 16mW, and it occupies a die area of 0.012mm^2 in standard 0.18µm CMOS technology. Finally, an analog calibration technique is discussed to lessen the mismatch between transistors in the differential high-frequency signal path of analog CMOS circuits. The proposed methodology involves auxiliary transistors that sense the existing mismatch as part of a feedback loop for error minimization. It was assessed by performing statistical Monte Carlo simulations of a differential amplifier and a double-balanced mixer designed in CMOS technologies