FOSS EKV2.6 Verilog-A Compact MOSFET Model

The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. The present paper provides a short review of foundations of the model and shows its capabilities via characterization and modeling based on a test chip in 180 nm CMOS fabricated via Europractice

Developing the knowledge-based human resources that support the implementation of the National Dual Training System (NDTS): evaluation of TVET teacher's competency at MARA Training Institutions

Development in the world of technical and vocational education and training (TVET) on an ongoing basis is a challenge to the profession of the TVET-teachers to maintain their performance. The ability of teachers to identify the competencies required by their profession is very critical to enable them to make improvements in teaching and learning. For a broader perspective the competency needs of the labour market have to be matched by those developed within the vocational learning processes. Consequently, this study has focused on developing and validating the new empirical based TVET-teacher competency profile and evaluating teacher’s competency. This study combines both quantitative and qualitative research methodology that was designed to answer all the research questions. The new empirical based competency profile development and TVET-teacher evaluation was based upon an instructional design model. In addition, a modified Delphi technique has also been adopted throughout the process. Initially, 98 elements of competencies were listed by expert panel and rated by TVET institutions as important. Then, analysis using manual and statistical procedure found that 112 elements of competencies have emerged from seventeen (17) clusters of competencies. Prior to that, using the preliminary TVET-teacher competency profile, the level of TVETteacher competencies was found to be Proficient and the finding of 112 elements of competencies with 17 clusters was finally used to develop the new empirical based competency profile for MARA TVET-teacher. Mean score analysis of teacher competencies found that there were gaps in teacher competencies between MARA institutions (IKM) and other TVET institutions, where MARA-teacher was significantly better than other TVET teacher. ANOVA and t-test analysis showed that there were significant differences between teacher competencies among all TVET institutions in Malaysia. On the other hand, the study showed that teacher’s age, grade and year of experience are not significant predictors for TVET-teacher competency. In the context of mastering the competency, the study also found that three competencies are classified as most difficult or challenging, twelve competencies are classified as should be improved, and eight competencies are classified as needed to be trained. Lastly, to make NDTS implementation a reality for MARA the new empirical based competency profile and the framework for career development and training pathway were established. This Framework would serve as a significant tool to develop the knowledge based human resources needed. This will ensure that TVET-teachers at MARA are trained to be knowledgeable, competent, and professional and become a pedagogical leader on an ongoing basis towards a world class TVET-education system

Characterization of optical interconnects

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.Includes bibliographical references (p. 72-75).Interconnect has become a major issue in deep sub-micron technology. Even with copper and low-k dielectrics, parasitic effects of interconnects will eventually impede advances in integrated electronics. One technique that has the potential to provide a paradigm shift is optics. This project evaluates the feasibility of optical interconnects for distributing data and clock signals. In adopting this scheme, variation is introduced by the detector, the waveguides, and the optoelectronic circuit, which includes device, power supply and temperature variations. We attempt to characterize the effects of the aforementioned sources of variation by designing a baseline optoelectronic circuitry and fabricating a test chip which consists of the circuitry and detectors. Simulations are also performed to supplement the effort. The results are compared with the performance of traditional metal interconnects. The feasibility of optical interconnects is found to be sensitive to the optoelectronic circuitry used. Variation effects from the devices and operating conditions have profound impact on the performance of optical interconnects since they introduce substantial skew and delay in the otherwise ideal system.by Shiou Lin Sam.S.M

New Mosfet Threshold Voltage Extraction Methods And Extractors

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2006Thesis (M.Sc.) -- İstanbul Technical University, Institute of Science and Technology, 2006MOSFET modellenmesinde çok önemli bir yer taşıyan eşik gerilimi, yapılan bir çok deneme sonucu matematiksel olarak hesaplanabilirken aynı zamanda çıkışında direk VTH’i veren basit devre yapıları ile de elde edilebilir. Bu çalışmada, kuvvetli-evirtim, lineer bölge, karakteristiklerine dayalı yeni eşik gerilimi elde etme yöntemleri önerilmiştir ve bu yöntemlere dayanarak çıkışlarında NMOS ve PMOS transistörler için eşik gerilimi veren devre yapılarının tasarımı anlatılmıştır. Önerlen yöntem temelde, analog bir yapı ile gerçeklenen aritmetik işlemin sonucuna dayandırılmıştır. Aritmetik işlem basit ve genelleştirilmiş olmak üzere iki yoldan incelenmiş ve bu yollardan her biri için üç farklı metod (IDPC,ICPD ve Esnek) önerilmiştir. Tasarlanan devrelerdeki mobilite etkisi, kanal boyu modülasyonu, boyut uyuşmazlığı ve gövde etkisi gibi ikinci dereceden etkiler analiz edilmiştir. Önerien devrelerde OPAMP, transistörleri linear bölgede kutuplamak, DDA ise çıkışında VTH’ı verecek olan aritmetik işlemi gerçeklemek için kullanılan yardımcı elemanlardır. Cadence-SpectreS ile yapılan ölçümler MOS transistörlerin eşik geriliminin tasarlanan yeni devreler ile % 1 veya % 0.8 hata ile elde edilebildiğini göstermiştir. NMOS eşik geriliminin sıcaklıkla negatif, PMOS eşik geriliminin sıcaklıkla pozitif olarak değişmesinden yararlanarak, sıcaklık katsayıları sırasıyla 1.9ْ9mV/Centigrade ve -1.42mV/Centigrade olan PTAT ve CTAT sıcaklık sensörler tasarlanmıştır. Yine aynı özellik yardımıyla OPAMP toplayıcı kullanılarak sıcaklık ve besleme gerilimi değişimlerinden bağımsız bir gerilim referans devresi elde edilmiştir.The threshold voltage value, which is the most important electrical parameter in modeling MOSFETs, can be extracted either from simulations or from the use of practical circuits which automatically and quickly yield the threshold voltage. In this thesis, new threshold voltage extraction methods based on the strong-inversion characteristic are proposed and the development of the NMOS and PMOS threshold voltage extractors implementing new methods is described. Proposed extraction method is based on an arithmetic operation which is classified into basic and generalized arithmetic operation schemes. Different implementations for each operation scheme such as IDPC, ICPD and Flexible method have been discussed and the effect of nonidealities such as mobility reduction, channel-length modulation, mismatch, and body effect has been analyzed. Auxiliary components are needed to perform design conditions. DDA operates as an arithmetic processor to precisely implement multiplication by two and subtraction as needed for extrapolation. OPAMP is also used to bias transistors in the linear region. The Cadence-SpectreS simulations confirm that threshold voltage of a MOS transistor can be extracted automatically using the VTH extractor without any need of calculation and delay. Additional applications such as temperature measurement, where the VTH extractor can be used either as a PTAT sensor or as a CTAT with small values of temperature coefficients (1.99mV/Centigrade and-1.42mV/Cent., respectively), and voltage reference circuit which is independent of temperature and supply voltage fluctuations, are presented.Yüksek LisansM.Sc

Phase Locked Loop Test Methodology

Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications

TSSOI as an efficient tool for diagnostics of SOI technology in Institute of Electron Technology, Journal of Telecommunications and Information Technology, 2005, nr 1

This paper reports a test structure for characterization of a new technology combining a standard CMOS process with pixel detector manufacturing technique. These processes are combined on a single thick-_lm SOI wafer. Preliminary results of the measurements performed on both MOS SOI transistors and dedicated SOI test structures are described in detail

Techniques of Energy-Efficient VLSI Chip Design for High-Performance Computing

How to implement quality computing with the limited power budget is the key factor to move very large scale integration (VLSI) chip design forward. This work introduces various techniques of low power VLSI design used for state of art computing. From the viewpoint of power supply, conventional in-chip voltage regulators based on analog blocks bring the large overhead of both power and area to computational chips. Motivated by this, a digital based switchable pin method to dynamically regulate power at low circuit cost has been proposed to make computing to be executed with a stable voltage supply. For one of the widely used and time consuming arithmetic units, multiplier, its operation in logarithmic domain shows an advantageous performance compared to that in binary domain considering computation latency, power and area. However, the introduced conversion error reduces the reliability of the following computation (e.g. multiplication and division.). In this work, a fast calibration method suppressing the conversion error and its VLSI implementation are proposed. The proposed logarithmic converter can be supplied by dc power to achieve fast conversion and clocked power to reduce the power dissipated during conversion. Going out of traditional computation methods and widely used static logic, neuron-like cell is also studied in this work. Using multiple input floating gate (MIFG) metal-oxide semiconductor field-effect transistor (MOSFET) based logic, a 32-bit, 16-operation arithmetic logic unit (ALU) with zipped decoding and a feedback loop is designed. The proposed ALU can reduce the switching power and has a strong driven-in capability due to coupling capacitors compared to static logic based ALU. Besides, recent neural computations bring serious challenges to digital VLSI implementation due to overload matrix multiplications and non-linear functions. An analog VLSI design which is compatible to external digital environment is proposed for the network of long short-term memory (LSTM). The entire analog based network computes much faster and has higher energy efficiency than the digital one