A Reconfigurable Tile-Based Architecture to Compute FFT and FIR Functions in the Context of Software-Defined Radio

Software-defined radio (SDR) is the term used for flexible radio systems that can deal with multiple standards. For an efficient implementation, such systems require appropriate reconfigurable architectures. This paper targets the efficient implementation of the most computationally intensive kernels of two significantly different standards, viz. Bluetooth and HiperLAN/2, on the same reconfigurable hardware. These kernels are FIR filtering and FFT. The designed architecture is based on a two-dimensional arrangement of 17 tiles. Each tile contains a multiplier, an adder, local memory and multiplexers allowing flexible communication with the neighboring tiles. The tile-base data path is complemented with a global controller and various memories. The design has been implemented in SystemC and simulated extensively to prove equivalence with a reference all-software design. It has also been synthesized and turns out to outperform significantly other reconfigurable designs with respect to speed and area

Wavelet-based response spectrum compatible synthesis of accelerograms-Eurocode application (EC8)

An integrated approach for addressing the problem of synthesizing artificial seismic accelerograms compatible with a given displacement design/target spectrum is presented in conjunction with aseismic design applications. Initially, a stochastic dynamics solution is used to obtain a family of simulated non-stationary earthquake records whose response spectrum is on the average in good agreement with the target spectrum. The degree of the agreement depends significantly on the adoption of an appropriate parametric evolutionary power spectral form, which is related to the target spectrum in an approximate manner. The performance of two commonly used spectral forms along with a newly proposed one is assessed with respect to the elastic displacement design spectrum defined by the European code regulations (EC8). Subsequently, the computational versatility of the family of harmonic wavelets is employed to modify iteratively the simulated records to satisfy the compatibility criteria for artificial accelerograms prescribed by EC8. In the process, baseline correction steps, ordinarily taken to ensure that the obtained accelerograms are characterized by physically meaningful velocity and displacement traces, are elucidated. Obviously, the presented approach can be used not only in the case of the EC8, for which extensive numerical results/examples are included, but also for any code provisions mandated by regulatory agencies. In any case, the presented numerical results can be quite useful in any aseismic design process dominated by the EC8 specifications

Communication Subsystems for Emerging Wireless Technologies

The paper describes a multi-disciplinary design of modern communication systems. The design starts with the analysis of a system in order to define requirements on its individual components. The design exploits proper models of communication channels to adapt the systems to expected transmission conditions. Input filtering of signals both in the frequency domain and in the spatial domain is ensured by a properly designed antenna. Further signal processing (amplification and further filtering) is done by electronics circuits. Finally, signal processing techniques are applied to yield information about current properties of frequency spectrum and to distribute the transmission over free subcarrier channels

Frame Theory for Signal Processing in Psychoacoustics

This review chapter aims to strengthen the link between frame theory and signal processing tasks in psychoacoustics. On the one side, the basic concepts of frame theory are presented and some proofs are provided to explain those concepts in some detail. The goal is to reveal to hearing scientists how this mathematical theory could be relevant for their research. In particular, we focus on frame theory in a filter bank approach, which is probably the most relevant view-point for audio signal processing. On the other side, basic psychoacoustic concepts are presented to stimulate mathematicians to apply their knowledge in this field

Synthesis of accelerograms compatible with the Chinese GB 50011-2001 design spectrum via harmonic wavelets: artificial and historic records

A versatile approach is employed to generate artificial accelerograms which satisfy the compatibility criteria prescribed by the Chinese aseismic code provisions GB 50011-2001. In particular, a frequency dependent peak factor derived by means of appropriate Monte Carlo analyses is introduced to relate the GB 50011-2001 design spectrum to a parametrically defined evolutionary power spectrum (EPS). Special attention is given to the definition of the frequency content of the EPS in order to accommodate the mathematical form of the aforementioned design spectrum. Further, a one-to-one relationship is established between the parameter controlling the time-varying intensity of the EPS and the effective strong ground motion duration. Subsequently, an efficient auto-regressive moving-average (ARMA) filtering technique is utilized to generate ensembles of non-stationary artificial accelerograms whose average response spectrum is in a close agreement with the considered design spectrum. Furthermore, a harmonic wavelet based iterative scheme is adopted to modify these artificial signals so that a close matching of the signals’ response spectra with the GB 50011-2001 design spectrum is achieved on an individual basis. This is also done for field recorded accelerograms pertaining to the May, 2008 Wenchuan seismic event. In the process, zero-phase high-pass filtering is performed to accomplish proper baseline correction of the acquired spectrum compatible artificial and field accelerograms. Numerical results are given in a tabulated format to expedite their use in practice

Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve

The Chameleon Architecture for Streaming DSP Applications

We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm$^2$ in a 130 nm process), is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC) via a network interface (NI). Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT) and best effort (BE). For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool

Measurements, Models, Systems and Design

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