Doctor of Philosophy

dissertationHigh speed wireless communication systems (e.g., long-term evolution (LTE), Wi-Fi) operate with high bandwidth and large peak-to-average power ratios (PAPRs). This is largely due to the use of orthogonal frequency division multiplexing (OFDM) modulation that is prevalent to maximize the spectral efficiency of the communication system. The power amplifier (PA) in the transmitter is the dominant energy consumer in the radio, largely because of the PAPR of the input signal. To reduce the energy consumption of the PA an amplifier that simultaneously achieves high efficiency and high linearity. Furthermore, to lower the cost for high volume production, it is desirable to achieve a complete System-on-Chip (SoC) integration. Linear amplifiers (e.g., Class-A, -B, -AB) are inefficient when amplifying signals with large PAPR that is associated by high peak-to-average modulation techniques such as LTE. OFDM. Switching amplifiers (e.g., Class-D, -E, -F) are very promising due to their high efficiency when compared to their linear amplifier counterparts. Linearization techniques for switching amplifiers have been intensively investigated due to their limited sensitivity to the input amplitude of the signal. Deep-submicron CMOS technology is mostly utilized for logic circuitry, and the Moore's law scaling of CMOS optimizes transistors to operate as high-speed and low-loss switches rather than high gain transistors. Hence, it is advantageous to use transistors in switching mode as switching amplifies and use high-speed digital logic circuitry to implement linearization systems and circuitry. In this work, several linearization architectures are investigated and demonstrated. An envelope elimination and restoration (EER) transmitter that comprises a class-E power amplifier and a 10-bit digital-to-analog converter (DAC) controlled current modulator is investigated. A pipelined switched-capacitor DAC is designed to control an open-loop transconductor that operates as a current modulator, modulating the amplitude of the current supplied to a class-E PA. Such a topology allows for increased filtering of the quantization noise that is problematic in most digital PAs (DPA). The proposed quadrature and multiphase architecture can avoid the bandwidth expansion and delay mismatch associated with polar PAs. The multiphase switched capacitor power amplifier (SCPA) was proposed after the quadrature SCPA and it significantly improves the power efficiency

High Efficiency Power Amplifier Based on Envelope Elimination and Restoration Technique

Due to complex envelope and phase modulation employed in modern transmitters it is necessary to use power amplifiers that have high linearity. Linear power amplifiers (classes A, B and AB) are commonly used, but they suffer from low efficiency especially if the transmitted signal has high peak to average power ratio (PAPR). Kahn's technique based on envelope elimination and restoration (EER) is based on idea that high efficiency power supply (envelope amplifier) could be used to modulate the envelope of high efficient non linear power amplifiers (classes D or E). This paper presents solutions for power amplifier that performs envelope modulation and class E amplifier that is used as a non linear amplifier. The envelope amplifier is implemented as a multilevel converter in series with linear regulator and can provide up to 100 W of instantaneous power and reproduce 2 MHz sine wave. The implemented Class E amplifier can operate at 120 MHz with efficiency near to 85%. The envelope amplifier and class E amplifier have been integrated and efficiency and linearity of the implemented transmitter has been measured and presente

Optimization Of 5.7 Ghz Class E Power Amplifier For The Application Of Envelope Elimination And Restoration

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2007Thesis (M.Sc.) -- İstanbul Technical University, Institute of Science and Technology, 2007Rekabetin yoğun olduğu günümüzde tasarımcılar hafif, boyutları daha küçük ve düşük güçle çalışan yüksek performanslı ürün geliştirmenin yollarını aramaktadırlar. RF alıcı uygulamalarında güç kuvvetlendiricileri en fazla güç sarfiyatının olduğu bölümdür. Kablosuz iletişim sistemlerinde güç küvvetlendiricisi verimi maliyeti direkt olarak etkilemektedir. Teorik olarak %100 verim elde edilebilen E-sınıfı güç kuvvetlendiricileri transistorların açık/kapalı durum geçişlerinde güç sarfiyatını minimize edebilmektedir. Ayrıca çıkış gerilimi kaynak gerilimi ile doğrusal değişmektedir. Bu çalışmada E sınıfı güç kuvvetlendiricilerinin tasarım metodları ele alınmıştır. 5.7 GHz de çalışan birinde toplu devre elemanları, diğerinde transmisyon hattı elemanları kullanımış E sınıfı güç kuvvetlendiricileri tasarlanmıştır. Her iki devrede de %50 güç ekli verim (GEV) ve 500mW çıkış gücü elde edilmiştir. Sinyaldeki bozulmayı azaltmak için başvurulan doğrusallaştırma yöntemi Zarf Yoketme ve Tekrar Oluşturma metodudur. E sınıfı kuvvetlendiricinin Zarf Yoketme ve Tekrar Oluşturma yöntemi kullanılarak doğrusallaştırılmasıyla IMD bileşenlerinde 7.5 dB azalmış olup seviyesi gerçek işaretin 20dB altındadır.In today’s competitive, manufactures and product developers are seeking ways to build high performance devices that are lighter in weight, smaller in size and operating at lower power. In transceiver applications one module is responsible for a large portion of the power consumption - the power amplifier. The efficiency of the power amplifier has a direct impact on the cost of the wireless communication system. The class-E amplifier has a maximum theoretical efficiency of 100%. Class E power amplifiers have the ability to minimize power loss during on/off transitions of the transistor. Also, the output voltage varies linearly with the supply voltage. This thesis describes the design and the linearization methodology of the Class E amplifiers. Two class-E amplifiers operating at 5.7 GHz are presented. One of them is a lumped elements based circuit and the other is a transmission lines based circuit. Both circuit show good performance with 50% PAE and have 500mW output power. Envelope elimination and restoration is the linearization method chosen to achieve reduction of signal distortion. Linearization Class E PA using EER system provides an additional 7.5 dB reduction in intermodulation distortion products, achieving a minimum distortion level of 20 dB below the fundamental signals.Yüksek LisansM.Sc

A linear assisted switching envelope amplifier for a UHF polar transmitter

Spectrally efficient wireless communication standards impose stringent linearity specifications, which would require traditional IQ transmitters to operate with back-offed and power inefficient linear RF power amplifiers (PAs). In order to overcome such a significant limitation, alternative architectures have been proposed, as those based on the envelope elimination and restoration technique. An example of the application of this technique is the polar transmitter. In this paper, a UHF polar transmitter is presented, combining switching and linear stages in the envelope amplifier as to achieve both wide bandwidth and high efficiency, when drain modulating a GaN HEMT Class E RF PA. Several tests, using EDGE, TETRA, and WCDMA standards have been performed with good results.This work was supported by the Spanish Ministries MICINN and MINECO through the FEDER cofunded Project TEC2011-29126-C03-01, Consolider Project CSD2008-00068, Consolider Project RUECSD2009-00046, and Project DPI2010-21110-C02-01

Energy Efficient RF Transmitter Design using Enhanced Breakdown Voltage SOI-CMOS Compatible MESFETs

abstract: The high cut-off frequency of deep sub-micron CMOS technologies has enabled the integration of radio frequency (RF) transceivers with digital circuits. However, the challenging point is the integration of RF power amplifiers, mainly due to the low breakdown voltage of CMOS transistors. Silicon-on-insulator (SOI) metal semiconductor field effect transistors (MESFETs) have been introduced to remedy the limited headroom concern in CMOS technologies. The MESFETs presented in this thesis have been fabricated on different SOI-CMOS processes without making any change to the standard fabrication steps and offer 2-30 times higher breakdown voltage than the MOSFETs on the same process. This thesis explains the design steps of high efficiency and wideband RF transmitters using the proposed SOI-CMOS compatible MESFETs. This task involves DC and RF characterization of MESFET devices, along with providing a compact Spice model for simulation purposes. This thesis presents the design of several SOI-MESFET RF power amplifiers operating at 433, 900 and 1800 MHz with ~40% bandwidth. Measurement results show a peak power added efficiency (PAE) of 55% and a peak output power of 22.5 dBm. The RF-PAs were designed to operate in Class-AB mode to minimize the linearity degradation. Class-AB power amplifiers lead to poor power added efficiency, especially when fed with signals with high peak to average power ratio (PAPR) such as wideband code division multiple access (W-CDMA). Polar transmitters have been introduced to improve the efficiency of RF-PAs at backed-off powers. A MESFET based envelope tracking (ET) polar transmitter was designed and measured. A low drop-out voltage regulator (LDO) was used as the supply modulator of this polar transmitter. MESFETs are depletion mode devices; therefore, they can be configured in a source follower configuration to have better stability and higher bandwidth that MOSFET based LDOs. Measurement results show 350 MHz bandwidth while driving a 10 pF capacitive load. A novel polar transmitter is introduced in this thesis to alleviate some of the limitations associated with polar transmitters. The proposed architecture uses the backgate terminal of a partially depleted transistor on SOI process, which relaxes the bandwidth and efficiency requirements of the envelope amplifier in a polar transmitter. The measurement results of the proposed transmitter demonstrate more than three times PAE improvement at 6-dB backed-off output power, compared to the traditional RF transmitters.Dissertation/ThesisPh.D. Electrical Engineering 201

Envelope amplifier based on switching capacitors for high efficiency RF amplifiers

Modern transmitters usually have to amplify and transmit signals with simultaneous envelope and phase modulation. Due to this property of the transmitted signal, linear power amplifiers (class A, B, or AB) are usually used as a solution for the power amplifier stage. These amplifiers have high linearity, but suffer from low efficiency when the transmitted signal has high peak-to-average power ratio. The Kahn envelope elimination and restoration technique is used to enhance the efficiency of RF transmitters, by combining highly efficient, nonlinear RF amplifier (class E) with a highly efficient envelope amplifier in order to obtain a linear and highly efficient RF amplifier. This paper presents a solution for the envelope amplifier based on a multilevel converter in series with a linear regulator. The multilevel converter is implemented by employing voltage dividers based on switching capacitors. The implemented envelope amplifier can reproduce any signal with a maximum spectral component of 2 MHz and give instantaneous maximum power of 50 W. The efficiency measurements show that when the signals with low average value are transmitted, the implemented prototypes have up to 20% higher efficiency than linear regulators used as a conventional solution

High Efficiency CMOS Power Amplifiers for Drain Modulation Based RF Transmitters

The rapid evolution of wireless communication technologies increased the need for handheld devices that can support dissimilar standards or better user mobility and more battery life. Traditional radio architectures fail to satisfy these challenging features. Software Defined Radio (SDR) is recently introduced to implement a new generation of wireless radios capable of coping with these stringent requirements through software reprogramming. Although the term SDR is widely used, it is still an idealized method and is not implementable using available technologies. Hence, the term “SDR”, has been so far, referring to only partially upgradeable radios. Two current practical solutions substituting SDR are broadband and multiband transceivers. Radio Frequency (RF) front ends and especially the power amplifier is the main challenge in implementation of software defined radios. Power Amplifiers (PA) dominate the sources of distortions and power consumption in the RF-front end. They are typically operated in linear classes in order to minimize the linearity degradation. However, they lead to poor average power efficiency especially when fed with signals with high Peak to average power ratio (PAPR) such as Wideband Code Division Multiple Access (W-CDMA) and Long Term Evolution (LTE) signals. This is the main cause of short battery life in transceivers. To remedy this issue, some advanced methods like Doherty amplifier and drain modulation based architectures are introduced. This thesis expounds on the implementation of high efficiency radio transmitters, capable of multi standard operation. The RF amplifier is still one of the main challenges in the realization of these transmitters. In this work, two RF PAs, having multiband and broad band characteristics, were implemented using 0.13µm CMOS technology. The first PA operates at two frequency bands, 2.4GHz and 3.5GHz. The other PA has center frequency equal to 2.4GHz and 600MHz bandwidth, respectively. These PAs are expected to lay the foundation for the realization of high efficiency drain modulation based multiband and broadband transmitters

High Efficiency Power Supplies for Multi-mode RF Power Amplifiers in Cellular Handset Applications

Cellular handset evolution requires the front end transmitter to support multiple 3G/4G bands for global roaming, and also to be backward compatible with the existing 2G (quad-band GSM/EDGE) network. The cost and size would be prohibitive if one power amplifier (PA) only supports one band or if multiple supplies are required for multiple PAs. Solutions of interest are based on multi-standard multi-band PAs (e.g. 2 multi-mode PAs instead of 8+ mode-specific PAs), and an efficient power supply that supports these multi-mode PAs. The thesis starts with a study of PA supply architectures and DC-DC converters. A series architecture consisting of a boost converter followed by a buck converter has advantages of low-noise buck converter output, together with the ability to deliver full power at low battery voltages to extend the battery life. The buck converter presents a constant power load for the boost converter, which raises stability concerns. Small-signal control-to-output transfer functions are derived for peak or valley current mode controlled boost converter with a downstream regulated converter modeled as constant power load. It is shown how current mode control provides active damping to ensure stability and well-behaved dynamic response. Furthermore, it is shown how load current feedforward presents an effective way to improve power load transient response. Modeling and design approaches are validated by test circuit simulations, demonstrating stable operations using current mode control under constant power loads, and improved power step load transient response based on load current feedforward. A buck/boost and LDO series architecture is proposed as the solution to address efficiency, linearity, noise and time mask requirements for the supplies supporting multi-standard, multi-band PAs. A monolithic integrated circuit (IC) has been designed and implemented in a standard 0.5 5V CMOS process for supplying the multi-mode PAs. The buck/boost converter with wide output range delivers the peak efficiency of 92%. The power LDO has 1-4 MHz bandwidth, to support the GSM/EDGE/WCDMA time mask requirements and the polar EDGE operation. The test chip consumes the quiescent current 1.1 mA, and it delivers maximum 5 W output