Study of voltage controlled oscillator based analog-to-digital converter

A voltage controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits. This thesis analyzes the performance of VCO-based ADCs in the presence of non idealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops. Based on this analysis, design criteria for determining parameters for VCO-based ADCs are described. Further, the study involves the use of VCO based Dual-slope A/D converter and its behaviour under different input voltage level. Graph is plotted between output voltages of the integrator vs. time. Digital circuits like a bit-counter and logic circuits are used for operation mode. A normal VCO model is also done in MATLAB-simulink environment and studied under variable input frequency and corresponding output plots are view

A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology

A novice advanced architecture of 8-bit analog todigital converter is introduced and analyzed in this work. Thestructure of proposed ADC is based on the sub-ranging ADCarchitecture in which a 4-bit resolution flash-ADC is utilized. Theproposed ADC architecture is designed by employing a comparatorwhich is equipped with common mode current feedback andgain boosting technique (CMFD-GB) and a residue amplifier. Theproposed 8 bits ADC structure can achieve the speed of 140 megasamplesper second. The proposed ADC architecture is designedat a resolution of 8 bits at 10 MHz sampling frequency. DNL andINL values of the proposed design are -0.94/1.22 and -1.19/1.19respectively. The ADC design dissipates a power of 1.24 mWwith the conversion speed of 0.98 ns. The magnitude of SFDRand SNR from the simulations at Nyquist input is 39.77 and 35.62decibel respectively. Simulations are performed on a SPICE basedtool in 90 nm CMOS technology. The comparison shows betterperformance for the proposed ADC design in comparison toother ADC architectures regarding speed, resolution and powerconsumption

Programmable CMOS Analog-to-Digital Converter Design and Testability

In this work, a programmable second order oversampling CMOS delta-sigma analog-to-digital converter (ADC) design in 0.5µm n-well CMOS processes is presented for integration in sensor nodes for wireless sensor networks. The digital cascaded integrator comb (CIC) decimation filter is designed to operate at three different oversampling ratios of 16, 32 and 64 to give three different resolutions of 9, 12 and 14 bits, respectively which impact the power consumption of the sensor nodes. Since the major part of power consumed in the CIC decimator is by the integrators, an alternate design is introduced by inserting coder circuits and reusing the same integrators for different resolutions and oversampling ratios to reduce power consumption. The measured peak signal-to-noise ratio (SNR) for the designed second order delta-sigma modulator is 75.6dB at an oversampling ratio of 64, 62.3dB at an oversampling ratio of 32 and 45.3dB at an oversampling ratio of 16. The implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ΔIDDQ testing of CMOS data converters is also presented. The BICS uses frequency as the output for fault detection in CUT. A fault is detected when the output frequency deviates more than ±10% from the reference frequency. The output frequencies of the BICS for various model parameters are simulated to check for the effect of process variation on the frequency deviation. A design for on-chip testability of CMOS ADC by linear ramp histogram technique using synchronous counter as register in code detection unit (CDU) is also presented. A brief overview of the histogram technique, the formulae used to calculate the ADC parameters, the design implemented in 0.5µm n-well CMOS process, the results and effectiveness of the design are described. Registers in this design are replaced by 6T-SRAM cells and a hardware optimized on-chip testability of CMOS ADC by linear ramp histogram technique using 6T-SRAM as register in CDU is presented. The on-chip linear ramp histogram technique can be seamlessly combined with ΔIDDQ technique for improved testability, increased fault coverage and reliable operation

Advanced digital modulation: Communication techniques and monolithic GaAs technology

Communications theory and practice are merged with state-of-the-art technology in IC fabrication, especially monolithic GaAs technology, to examine the general feasibility of a number of advanced technology digital transmission systems. Satellite-channel models with (1) superior throughput, perhaps 2 Gbps; (2) attractive weight and cost; and (3) high RF power and spectrum efficiency are discussed. Transmission techniques possessing reasonably simple architectures capable of monolithic fabrication at high speeds were surveyed. This included a review of amplitude/phase shift keying (APSK) techniques and the continuous-phase-modulation (CPM) methods, of which MSK represents the simplest case

Design of a SRAM memory controller and interface for in-memory computing applications

Recently, neural networks have gained much attention, due to their high effectiveness. Their operation principle is based on massively parallel calculations, which possess a challenge for classical computing architectures, based on the Von Neumann principle, which uses separate memory and computing units. Due to low throughput of interconnections between these two systems (the so called Von-Neumann bottleneck) neural net-works cannot be effectively computed by these classical architectures. Therefore, many in-memory-computing architectures, where many computations are performed inside memory, have been recently proposed to solve this issue. In-memory-computing system provides efficient implementation of massively parallel computation. However, providing necessary weights of neural networks into the computing units poses challenges, as memory is typically too small to fit all weights and perform all computations at once. Yet, finding efficient ways of loading weights into this memory has not been extensively researched. For that reason, this thesis focuses on design of memory controller, that is used in in-memory-computing architecture for transferring weights into the under-lying memory. Specifically, several controller topologies are compared, and one selected design is simulated in the context of an in-memory computing matrix. In addition, this thesis provides an extensive theory background of IMC system, namely its variations, basic building blocks, advantages and disadvantages

Low Noise Time to Digital Converters as Phase Detectors for All Digital PLLs

Nowadays PLLs are used in in almost every electronic circuit, because phase correction and detection are very important in a circuit. For this phase detection TDCs are used. This work proposes and demonstrates a Low noise Time to Digital Converter (TDC). This Time to Digital converter will be used as a phase detector in an all Digital PLL, with a 100 MHz frequency. The proposed topology employs CMOS inverters, and Set and Reset Flip Flops, due to their simplicity, to achieve a 4 bit circuit. The performance of the circuit was studied by evaluation fundamental parameters like RMS jitter, linearity, resolution and range. To further test the circuit a mismatch and noise analysis was performed, by testing the circuit with the PVT corners and Monte Carlo variations. The proposed TDC is simulated, using UMC 130 nm CMOS technology, achieves a RMS jitter of 22.9 f s, a INL and DNL error of 0.13 and 0.11 LSB respectively and a resolution of 15.3 ps. The TDC also has a power consumption of 1.11 mW and a area of 0.143 mm2.Atualmente as PLLs são utilizadas em quase todos os circuitos eletrónicos, porque a correção e a deteção de fase são muito importantes num circuito. Para esta deteção de fase são utilizados CTDs. Este trabalho propõe e demonstra um conversor de tempo para digital (CTD) de baixo ruído. Este conversor de tempo para digital será utilizado como detetor de fase num PLL completamente Digital, com frequência de 100 MHz. A topologia proposta emprega inversores CMOS e Flip Flops Set e Reset, devido à sua simplicidade, para obter um circuito de 4 bits. O desempenho do circuito foi estudado pela avaliação de parâmetros fundamentais como jitter RMS, linearidade, resolução e alcance. Para testar ainda mais o circuito foi realizada uma análise de incompatibilidade e ruído, testando o circuito com os cantos PVT e variações de Monte Carlo. O CTD proposto é simulado, usando tecnologia UMC 130 nm CMOS, atinge um jitter RMS de 22,9 f s, um erro INL e DNL de 0,13 e 0,11 LSB respetivamente e uma resolução de 15,3 ps. O CTD tem também um consumo de energia de 1,11 mW e uma área de 0.143 mm2