A Multi-Gigahertz Analog Transient Recorder Integrated Circuit

A monolithic multi-channel analog transient recorder, implemented using switched capacitor sample-and-hold circuits and a high-speed analogically-adjustable delay-line-based write clock, has been designed, fabricated and tested. The 2.1 by 6.9 mm layout, in 1.2 micron CMOS, includes over 31,000 transistors and 2048 double polysilicon capacitors. The circuit contains four parallel channels, each with a 512 deep switched-capacitor sample-and-hold system. A 512 deep edge sensitive tapped active delay line uses look-ahead and 16 way interleaving to develop the 512 sample and hold clocks, each as little as 3.2 ns wide and 200 ps apart. Measurements of the device have demonstrated 5 GHz maximum sample rate, at least 350 MHz bandwidth, an extrapolated rms aperture uncertainty per sample of 0.7 ps, and a signal to rms noise ratio of 2000:1.Comment: 64 pages, 17 figures. Thesis, University of California, Berkeley, 199

Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections

Redundant analog to digital conversion architectures in CMOS technology

The operation of modern electronic devices in different fields as communications, signal processing, and sensor interface is critically affected with robust, high performance and scalable Analog-to-Digital Converter (ADCs), that can be considered as one of the main blocks in many systems, since they are mandatory to make the link between the analog outside world and the evermore-ubiquitous digital computer world. The design of these ADCs come distinct tradeoffs between speed, power, resolution, and die area embodied within many data conversion architectural variations. The flash ADC structure are often the base structure for high-speed operation and simple architecture analog-to-digital converters (ADCs). As the input signal is applied to (

Redundant analog to digital conversion architectures in CMOS technology

The operation of modern electronic devices in different fields as communications, signal processing, and sensor interface is critically affected with robust, high performance and scalable Analog-to-Digital Converter (ADCs), that can be considered as one of the main blocks in many systems, since they are mandatory to make the link between the analog outside world and the evermore-ubiquitous digital computer world. The design of these ADCs come distinct tradeoffs between speed, power, resolution, and die area embodied within many data conversion architectural variations. The flash ADC structure are often the base structure for high-speed operation and simple architecture analog-to-digital converters (ADCs). As the input signal is applied to (

Low power VCO-based analog-to-digital conversion

textThis dissertation presents novel two stage ADC architecture with a VCO based second stage. With the scaling of the supply voltages in modern CMOS process it is difficult to design high gain operational amplifiers needed for traditional voltage domain two-stage analog to digital converters. However time resolution continues to improve with the advancement in CMOS technology making VCO-based ADC more attractive. The nonlinearity in voltage-to-frequency transfer function is the biggest challenge in design of VCO based ADC. The hybrid approach used in this work uses a voltage domain first stage to determine the most significant bits and uses a VCO based second stage to quantize the small residue obtained from first stage. The architecture relaxes the gain requirement on the the first stage opamp and also relaxes the linearity requirements on the second stage VCO. The prototype ADC built in 65nm CMOS process achieves 63.7dB SNDR in 10MHz bandwidth while only consuming 1.1mW of power. The performance of the prototype chip is comparable to the state-of-art in terms of figure-of-merit but this new architecture uses significantly less circuit area.Electrical and Computer Engineerin

Some Application of Switched Current Circuits.

A complete digital signal processing system requires analog circuits acting as an interface between the digital system and the outside analog world. Various techniques have been proposed to implement these circuits, but the one compatible with digital technology is switched capacitor (SC) technique. However, there are still some problems with SC circuits which are as follows: (i) The process technology used for these circuits is not compatible with the standard digital process technology due to extra poly-silicon layer, (ii) the performance of these circuits worsens for low voltage operations, because lower supply voltage will tend to increase power consumption for the same dynamic range, and in order to maintain the same dynamic range on a low supply voltage requires a quadratic increase in sampling capacitance to reduce thermal noise. The required increase in bias current to maintain circuit bandwidth results in a net increase in the overall power consumption. To overcome these problems, a new technique called the switched current (SI) technique has been proposed. The technique utilizes the ability of an MOS transistor to maintain its drain current, when its gate is open circuited, through the charge stored on its gate oxide capacitance. In this technique signals are represented by currents instead of voltages and, therefore, the signal swing is only indirectly limited by a reduction of the available voltage range. In a traditional voltage mode circuit, the supply voltage imposes a direct limitation on signal swing. Switched current circuits could therefore be a better for low voltage operation. 5 The application of switched current systems is much same as for switched capacitor systems viz. filters, A/D and D/A converters, general signal processing etc. but the prime aim is that switched current circuits should be implemented using a standard VLSI. In this work, the SI technique has been studied and several reported SI circuits have been simulated for their performance. Specifically, the work was aimed at the study of developing SI technique for the design of high performance circuits such as Integrators, Differentiators, Programmable filters, A/D and D/A converters, Sigma Delta Modulators, Multipliers, Delays etc. All the investigations are based on the PSPICE simulations using model parameters of the BISIM335 MOS transistors. The investigations match the theoretical interpretations and predictions. The entire gamut of this dissertation has been to study the already reported SI circuits and to investigate them for improved accuracy, dynamic range, bandwidth, linearity and low voltage operation

An Ultra Low Power Digital to Analog Converter Optimized for Small Format LCD Applications

Liquid crystal displays (LCDs) for mobile applications present a unique design challenge. These small format displays can be found primarily in cell phones and PDAs which are devices that have particularly stringent power requirements. At the same time, the displays are increasing in resolution with every generation. This is creating demand for new LCD display technologies. The predominant amorphous thin film transistor technology is no longer feasible in the new high resolution small format screens due to the fact that the displays require too many connections to the driver and the aperture ratios do not allow high density displays. New technologies such as low temperature polysilicon (LTPS) displays continue to shrink in size and increase in resolution. LTPS technology enables the display manufacturer to create relatively high quality transistors on the glass. This allows for a display architecture which integrates the gate driver on the glass. Newer LTPS LCDs also enable a high level of multiplexing the sources lines on the glass which allows for a much simpler connection to the display driver chip. The electronic drivers for these display applications must adhere to strict power and area budgets. This work describes a low-power, area efficient, scalable, digital-to-analog conversion (DAC) integrated circuit architecture optimized for driving small format LCDs. The display driver is based on a twelve channel, 9-bit DAC driver. This architecture, suitable for % VGA resolution displays, exhibited a 2 MSPS conversion rate, less than 300 pW power dissipation per channel using a 5 V supply, and a die area of 0.042 mm per DAC. A new performance standard is set for DAC display drivers in joules per bit areal density