Reduction of acoustic feedback oscillations by use of spectrum shifting

The problem of whistling noise or self-oscillation in public address systems operating in closed halls or rooms can be very disturbing to the listeners. This noise is sustained when the positive acoustic feedback, of the public address-room system, meets the oscillation criteria. This feedback system results from the acoustic sound signal reflected off the room walls and any other obstacles in the room, originating from the public address speakers and then re-entering the microphone. When all of the audio signal components entering the public address system are shifted by a frequency increment Δf of 6 Hz, an increase of 5 dB in the useable signal level was achieved and whistling noise reduction is attained. This thesis describes an apparatus for frequency shifting by small increments in steps of 1 Hz. The system is of simple implementation and effectively reduces the whistling noise and increases the value of achievable gain without introducing any speech distortions. While the idea turned out to be not original, since it was described in the early sixties, the time for it may be now, because integrated circuits made it feasible in terms of cost, size and portability. Due to this, we feel that reintroducing the idea at this time may be fortuitous

Accurate Phase Calibration for Digital Beam-Forming in Multi-Transceiver HF Radar System

The TIGER-3 radar is being developed as an “all digital” radar with 20 integrated digital transceivers, each connected to a separate antenna. Using phased array antenna techniques, radiated power is steered towards a desired direction based on the relative phases within the array elements. This paper proposes an accurate phase measurement method to calibrate the phases of the radio output signals using Field Programmable Gate Array (FPGA) technology. The method sequentially measures the phase offset between the RF signal generated by each transceiver and a reference signal operated at the same frequency. Accordingly, the transceiver adjusts its phase in order to align to the reference phase. This results in accurately aligned phases of the RF output signals and with the further addition of appropriate phase offsets, digital beamforming (DBF) can be performed steering the beam in a desired direction. The proposed method is implemented on a Virtex-5 VFX70T device. Experimental results show that the calibration accuracy is of 0.153 degrees with 14 MHz operating frequency

Implementation of a software defined radio on FPGAs using system generator

The aim of this thesis is to implement a Software Defined Radio based wireless communication system using a Xilinx Spartan 3E Field Programmable Gate Array. Software Defined Radio refers to the class of reprogrammable radios in which the same piece of hardware can perform different functions at different times. Xilinx’s System Generator for Digital Signal Processor tool is used to simulate and implement AM modulation on the Spartan 3E Starter Board. The aim of this thesis is to implement a Software Defined Radio based wireless communication system using a Xilinx Spartan 3E Field Programmable Gate Array. Software Defined Radio refers to the class of reprogrammable radios in which the same piece of hardware can perform different functions at different times. Xilinx’s System Generator for Digital Signal Processor tool is used to simulate and implement AM modulation on the Spartan 3E Starter Board

Space Communication Channel Emulation Using Digital and Analog Signal Processing

New communication protocols intended for large distances, including low orbit and deep space, can be inherently difficult to evaluate since trial implementations are often impractical. In order to accurately measure the performance of a new protocol, it is important to evaluate it in an environment that most closely matchs that in which it will be used. This thesis demonstrates the ability to emulate a space communications channel through digitizing a transmission centered at an intermediate frequency of 70 MHz with a bandwidth of 24 MHz, digitally introducing the characteristics of a transmission through space, and reconstructing the digital data to its analog counterpart. Delay, Doppler shift, Gaussian noise, and fading are among the most prevalent characteristics of such a channel, and thus were the focus of this thesis. Special care was given to the design of each digital and analog component to maintain the integrity of the original signal by minimizing all undesired noise introduced. The final design can accurately produce a given dynamic transmission signature or continually output a static set of channel characteristic parameters to test new communication protocols

Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA)

Direct digital synthesis is a technique for using digital data processing blocks as a means to generate a frequency and phase tunable output signal referenced to a fixed-frequency precision clock source. Many telecommunication applications require such a high-speed switching, fine- tuning and superior quality signal source for their components. This thesis will introduce the direct digital synthesizer (DDS) and investigate the signal integrity issues associated with the DDS design. In order to minimize the size of the lookup table to save hardware and lower the power consumption, we normally truncate the phase word output from the phase accumulator in the standard approach of designing DDS. However, this process will generate spurious frequencies (spurs), which degrade the quality of the output signals. It is considered one of the main signal integrity issues in the DDS design. Previous research introduces a novel spurs-free truncation method for compressing the lookup table to avoid using phase truncation without significant hardware change. This thesis aims to implement this DDS with novel truncation spurs-free structure and test it in a practical environment. It does so by providing a tutorial on designing, implementing and simulating the DDS on an Altera DE2-115 FPGA using Altera Quartus II FPGA design software and ModelSim Simulator. The Verilog hardware description language is used as the development language. This thesis will describe entire designs of both DDS with traditional structure and DDS with novel truncation spurs-free structure. By comparing the outputs, it also examines the corresponding simulation results and verifies the improvement of the signal quality

A built-in self-test technique for high speed analog-to-digital converters

Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009

Under Water Acoustic Modem Design

We present a reconfigurable modem for underwater acoustic communication, using BPSK modulation with coherent detection. The modem is capable of throughput up to 16 kbps in the 1- 2 MHz band, while being a flexible platform for deployment in a variety of scenarios, with realtime parameters to optimize communication with respect to channel conditions. In order to maximize the flexibility the system was implemented on an FPGA, so that the implementation can be changed during operation. The transmitter was designed mainly for compactness, using a digital direct synthesizer and IP CORE generator technique to generate the output signal. Phase synchronization technique is adopted for the recovery of transmitted data at the receiver sectio