Analytical Modeling of Ultrashort-Channel MOS Transistors

Les geometries de transistors d'avui són al rang de nanòmetres d'un sol dígit. En conseqüència, les funcionalitats dels dispositius es veuen afectades negativament pels efectes de canal curt i de mecànica quàntica (SCE i QMEs). Una transició de la geometria del transistor d'efecte de camp de tipus FinFET a Gate-All-Around (GAA) FETs com FETs de nanofils cilíndrics (NW) i de nanoplaques de silici (SiNS) es preveuen en els propers nodes tecnològics per suprimir els SCE i garantir una major miniaturització del MOSFET Aquesta dissertació se centra en el modelat analític de FETs de tipus NW i SiNS de canal ultracurt.S'introdueix un concepte de dimensions de doble porta (DG) equivalent per transferir un model de potencial de DG analític a FET de NW. Un model de corrent de DG compacte es modifica aprofitant la simetria rotacional dels FET de NW. L'efecte del confinament quàntic (QC) és implementat considerant l'eixamplament addicional de la banda prohibida al càlcul d'una concentració de portadors de càrrega intrínseca efectiva i al càlcul del voltatge llindar. L'efecte de corrent túnel directe de font a drenador (DSDT) a SiNS FET ultraescalats es modela amb el nou mètode de wavelets. Aquest model calcula analíticament la probabilitat de tunelització per a cada energia de l'electró, aproximant la forma de la barrera potencial mitjançant una barrera rectangular amb una altura de barrera equivalent. A causa de la fórmula de corrent túnel de Tsu-Esaki no analíticament integrable, es presenta un mètode analític anomenat model quasi-compacte (QCM). Aquest enfocament requereix, entre altres aproximacions, una iteració de Newton i una interpolació lineal de la densitat de corrent amb efecte túnel. A més, es realitza una anàlisi criogènica de temperatura i dopatge. S'investiga la forta influència de la distància del nivell de Fermi a la font des de la vora de la banda de conducció sobre el pendent subumbral, el corrent i la reducció de la barrera induïda per drenador (DIBL). A més, es demostra i explica la fusió de dos efectes relacionats amb el pendent subumbral i el DIBL. La validesa del concepte de dimensions DG equivalents es demostra mitjançant el mesurament i les dades de simulació de TCAD Sentaurus, mentre que el mètode de wavelets es verifica mitjançant simulacions NanoMOS NEGF.Las geometrías de transistores de hoy están en el rango de nanómetros de un solo dígito. En consecuencia, las funcionalidades de los dispositivos se ven afectadas negativamente por los efectos de canal corto y de mecánica cuántica (SCE y QMEs). Una transición de la geometría del transistor de efecto de campo de tipo FinFET a Gate-All -Around (GAA) FETs tales como FETs de nanohilos cilíndricos (NW) y de nanoplacas de silicio (SiNS) se prevén en los próximos nodos tecnológicos para suprimir los SCE y garantizar una mayor miniaturización del MOSFET. Esta disertación se centra en el modelado analítico de FETs de tipo NW y SiNS de canal ultracorto. Se introduce un concepto de dimensiones de doble puerta (DG) equivalente para transferir un modelo de potencial de DG analítico a FET de NW. Un modelo de corriente de DG compacto se modifica aprovechando la simetría rotacional de los FET de NW. El efecto del confinamiento cuántico (QC) es implementado considerando el ensanchamiento adicional de la banda prohibida en el cálculo de una concentración de portadores de carga intrínseca efectiva y en el cálculo del voltaje de umbral. El efecto de corriente túnel directa de fuente a drenador (DSDT) en SiNS FET ultraescalados se modela con el nuevo método de wavelets. Este modelo calcula analíticamente la probabilidad de tunelización para cada energía del electrón aproximando la forma de la barrera de potencial mediante una barrera rectangular con una altura de barrera equivalente. Usando la fórmula de corriente túnel de Tsu-Esaki no analíticamente integrable, se presenta un método analítico denominado modelo cuasi-compacto (QCM), querequiere una iteración de Newton y una interpolación lineal de la densidad de corriente de efecto túnel. Además, se realiza un análisis criogénico en temperatura y dopaje. Se investiga la fuerte influencia del nivel de Fermi de la fuente la sobre la pendiente subumbral, la corriente y la reducción del efecto DIBL. Además, se demuestra y explica la fusión de dos efectos relacionados con la pendiente subumbral y el DIBL. La validez del concepto de dimensiones DG equivalentes se demuestra mediante datos de mediciones y de simulaciones TCAD Sentaurus, mientras que el método de wavelets se verifica mediante simulaciones NanoMOS NEGF.Today's transistor geometries are in the single-digit nanometer range. Consequently, device functionalities are negatively affected by short-channel and quantum mechanical effects (SCEs & QMEs). A transition from fin field-effect transistor (FinFET) geometry to gate-all-around (GAA) FETs such as cylindrical nanowire (NW) and silicon nanosheet (SiNS) FETs is envisioned in the upcoming technology nodes to suppress SCEs and ensure further MOSFET miniaturization. This dissertation focuses on the analytical modeling of ultrashort-channel NW and SiNS FETs. An equivalent double-gate (DG) dimensions concept is introduced to transfer an analytical DG potential model to NW FETs. A compact DG current model is modified by exploiting the rotational symmetry of NW FETs. The effect of quantum confinement (QC) is implemented by considering the additional bandgap widening in the calculation of an effective intrinsic charge carrier concentration and in the calculation of the threshold voltage. The effect of direct source-to-drain tunneling (DSDT) current in ultrascaled SiNS FETs is modeled with the new wavelet approach. This model calculates the tunneling probability analytically for each electron energy by approximating the potential barrier shape by a rectangular barrier with an equivalent barrier height. Due to the nonanalytically integrable Tsu-Esaki tunneling formula an analytical approach named quasi-compact model (QCM) is presented. This approach requires, among other approximations, a Newton iteration, and a linear interpolation of the tunneling current density. Furthermore, a cryogenic temperature and doping analysis is performed. The strong influence of the distance of the source related Fermi level from the conduction band edge on the subthreshold swing, current, and drain-induced barrier lowering (DIBL) saturation is investigated. Also, the merging of two subthreshold swing and DIBL effects is demonstrated and explained. The validity of the equivalent DG dimensions concept is proven by measurement and TCAD Sentaurus simulation data, while the wavelet approach is verified by NanoMOS NEGF simulations

Two dimensional quantum and reliability modelling for lightly doped nanoscale devices

The downscaling of MOSFET devices leads to well-studied short channel effects and more complex quantum mechanical effects. Both quantum and short channel effects not only alter the performance but they also affect the reliability. This continued scaling of the MOS device gate length puts a demand on the reduction of the gate oxide thickness and the substrate doping density. Quantum mechanical effects give rise to the quantization of energy in the conduction band, which consequently creates a larger effective bandgap and brings a displacement of the inversion layer charge out of the Si/SiO2 interface. Such a displacement of charge is equivalent to an increase in the effective oxide layer thickness, a growth in the threshold voltage, and a decrease in the current level. Therefore, using the classical analysis approach without including the quantum effects may lead to perceptible errors in the prognosis of the performance of modern deep submicron devices. In this work, compact Verilog-A compatible 2D models including quantum short channel effects and confinement for the potential, threshold voltage, and the carrier charge sheet density for symmetrical lightly doped double-gate MOSFETs are developed. The proposed models are not only applicable to ultra-scaled devices but they have also been derived from analytical 2D Poisson and 1D Schrodinger equations including 2D electrostatics, in order to incorporate quantum mechanical effects. Electron and hole quasi-Fermi potential effects were considered. The models were further enhanced to include negative bias temperature instability (NBTI) in order to assess the reliability of the device. NBTI effects incorporated into the models constitute interface state generation and hole-trapping. The models are continuous and have been verified by comparison with COMSOL and BALMOS numerical simulations for channel lengths down to 7nm; very good agreement within ±5% has been observed for silicon thicknesses ranging from 3nm to 20nm at 1 GHz operation after 10 years

Analitical modeling for square gate-all-around MOSFETs

Two analytical models for square Gate All Around (GAA) MOSFETs has been introduced. The first part of this report include a quantum viewpoint and this first work has been published, while the second part approach a classical developed. With the model developed in the first part, it is possible to provide an analytical description of the 2D inversion charge distribution function (ICDF) in square GAA MOSFETs of difeerent sizes and for all the operational regimes. The accuracy of the model is verified by comparing the data with that obtained by means of a 2D numerical simulator that self-consistently solves the Poisson and Schrödinger equations. The expressions presented here are useful to achieve a good description of the physics of these transistors; in particular, of the quantization effects on the inversion charge. The analytical ICDF obtained is used to calculate important parameters from the device compact modeling viewpoint, such as the inversion charge centroid and the gate-to-channel capacitance, which are modeled for different device geometries and biases. The model presented accurately reproduces the simulation results for the devices under study and for different operational regimes. Anyway the second part of this report is focus on square GAA MOSFETs with a classical view point, which have not been analytically described in depth due to their particular geometrical complexity. The analytical description of cylindrical GAA MOSFETs is simpler since the symmetry of the structure around the rotation angle allows a 1D description, accounting just for the radial component. In the case of square GAA MOSFETs other modeling strategies are necessary, as will be shown below. Firstly, a technique to obtain analytical functions which are solutions of the 2D Poisson equation where the charge density in the silicon channel has been calculated, and the total inversion charge is introduced. Among all these functions a simple one for the electric potential in the silicon core of the square GAA MOSFETs was proposed. Secondly, the model introduced has been used to calculate the total inversion charge making use of Gauss's Law. The models obtained are finally validated with simulations data obtained with a 2D simulator developed in our group for Multiple-gate MOSFETs.Universidad de Granada. Departamento de Electrónica y Tecnología de los Computadores. Máster Métodos y Técnicas Avanzadas en Física (MTAF)This work was partially carried out within the framework of Research Projects of Department of Electronic and Computer Technology from the Faculty of Sciences, University of Granada

A 2-D/3-D Schrödinger-Poisson Drift-Diffusion Numerical Simulation of Radially-Symmetric Nanowire MOSFETs

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Local volume depletion/accumulation in GAA Si nanowire junctionless nMOSFETs

In this paper, we report, for the first time, corner effect analysis in the gate-all-around equilateral triangular silicon nanowire (NW) junctionless (JL) nMOSFETs, from subthreshold to strong accumulation regime. Corners were found to accumulate and deplete more electrons than the flat sides or the channel center, when above (local accumulation) and below (local depletion) the flat-band voltage, respectively. On the contrary to the corner effect in the inversion mode (IM) devices, there is no major contribution of corners in the subthreshold current, and therefore, there is no subthreshold device behavior degradation (only one threshold voltage in the system). N-type channel doping levels of 1 x 10(19), 5 x 10(18), and 1 x 10(18) cm(-3) were used for quasi-stationary device simulations of JL and AMMOSFETs, and corner effect was studied for 5, 10, and 15 nm wide equilateral triangular Si NW MOSFETs with a 2 nm SiO2 gate oxide thickness (V-DS = 0 V; T = 300 K). While the local quantum and classical electron density peaks are located in the corner regions above the flat-band voltage, reducing the channel doping and the channel cross-section was found to slightly suppress the normalized total accumulation electron density per unit length, N-acc(t)/(CWeff), in strong accumulation regime

Design evolution of dual-material gate structure in cylindrical surrounding double-gate (CSDG) MOSFET using physics-based analytical modeling.

Doctoral Degree. University of KwaZulu- Natal, Durban.The Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is the fundamental component in present Micro and Nano-electronics device applications, such as switching, memory devices, communication devices, etc. MOSFET’s dimension has shrunk down following Moore’s law to attain high-speed operation and packing density integration. The scaling of conventional MOSFET has been the most prominent technological challenge in the past few years because the decreasing device dimensions increase the charge sharing from the source to the drain and that in turn give rises to the reduced gate-control over the channel, hot carrier induced degradation, and other SCEs. These undesired effects devaluate the device performance that compels optimum device design analysis for particular operating conditions. Therefore, several innovative device design/architectures, including Double-gate, FinFET, Surrounding gate MOSFET, etc., have been developed to mitigate device scaling challenges. Comprehensive research can be traced long for one such promising gate-all-around MOSFET, i.e., Cylindrical Surrounding Double-Gate (CSDG) MOSFET centrally hollow concentric structure, provides an additional internal control gate that improves the device electrical performance and offers easy accessibility. There have been several developments in terms of improvements, and applications of CSDG MOSFET have been practiced since after its evolution. This thesis’s work has been targeted to incorporate the gate material engineering in the CSDG structure after appropriate analysis of device physics-based modeling. In particular to the proposed structure, the electric field, pinch off capacitance, and after that thickness of the device parameters’ dependence have been mathematically derived from attaining the objective. Finally, a model based on a dual-material gate in CSDG MOSFET has been proposed. The electrical field in CSDG MOSFET has been analyzed in detail using a mathematical derivation of device physics, including the Surface-Potential, threshold voltage, and the gate-oxide capacitances of the internal and external part of the device. Further, the gate-oxide capacitance of CSDG MOSFET, particularly to the device pinch-off condition, has been derived. Since the device operation and analysis at the shorter channel are not similar to conventional long-channel MOSFETs, the depletion-width variation has been studied. The identified notion has been applied to derive the approximate numerical solution and silicon thickness inducing parameters for CSDG MOSFET to deploy the improvements in the device performance and novel design modifications. As the gate-material and gate-stack engineering is an alternative to overcome the device performance degradation by enhancing the charge transport efficiency, the CSDG MOSFET in a novel Dual-Metal Gate (DMG) structure design has been proposed and analyzed using the solution of 2D Poisson’s equations in the geometrical boundary conditions of the device. The model expressions obtained solution using the proposed structure has been compared with a single metal gate structure. Finally, it has been analyzed that the proposed model exhibits an excellent match with the analytical model. The obtained DMG device structure advances the carrier velocity and transport efficiency, resulting in the surface-potential profile caused by dissimilar gate metal work-function. The superior device characteristics obtained employing a dual-material structure in CSDG are promising and can reduce the threshold voltage roll-off, suppress the hot-carrier effects and SCEs

3-D Quantum Numerical Simulation of Transient Response in Multiple-Gate Nanowire MOSFETs Submitted to Heavy Ion Irradiation

International audienc

Multi-gate Si nanowire MOSFETs:fabrication, strain engineering and transport analysis

Multi-gate devices e.g. gate-all-around (GAA) Si nanowires and FinFETs are promising can- didates for aggressive CMOS downscaling. Optimum subthreshold slope, immunity against short channel effect and optimized power consumption are the major benefits of such archi- tectures due to higher electrostatic control of the channel. On the other hand, Si nanowires show excellent mechanical properties e.g. yield and fracture strengths of 10±2% and 30±1% in comparison to 3.7% and 4.0% for bulk Si, respectively, a strong motivation to be used as exclusive platforms for innovative nanoelectronic applications e.g. novel strain engineering techniques for carrier transport enhancement in multi-gate 3D suspended channels or lo- cal band-gap modulation using > 4 GPa uniaxial tensile stress in suspended Si channels to enhance the band-to-band tunneling current in multi-gate Tunnel-FETs, all without plastic deformation and therefore, no carrier mobility degradation in deeply scaled channels. In this thesis and as a first step, a precise built-in stress analysis during local thermal oxidation of suspended Si NWs in the presence of a Si3N4 tensile hard mask was done. Accumulation of up to 2.6 GPa uniaxial tensile stress in the buckled NWs is reported. The contribution of hard mask/spacer engineering on the stress level and the NW formation was studied and buckled self-aligned dual NW MOSFETs on bulk Si with two sub-100 nm cross-sectional Si cores including ∼0.8 uniaxial tensile stress are reported. Micro-Raman spectroscopy was widely used in this thesis to measure stress in the buckled NWs on both bulk and SOI substrates. A process flow was designed to make dense array of GAA sub-5 nm cross-sectional Si NWs using a SOI substrate including a high level of stress. The NW stress level can be engineered simply using e.g. metal-gate thin film stress suitable for both NMOS and PMOS devices. Lately, highly and heavily doped architectures with a single-type doping profile from source to drain, called junctionless and accumulation-mode devices, are proposed to significantly simplify the fabrication process, address a few technical limitations e.g. ultra-abrupt junctions in order to fabricate shorter channel length devices. Therefore, in this process flow, a highly doped accumulation-mode was targeted as the operation mechanism. Finally, extensive TCAD device simulation was done on GAA Si NW JL MOSFETs to study the corner effects on the device characteristics, from subthreshold to strong accumulation, report the concept of local volume accumulation/depletion, quantum flat-band voltage, significant bias-dependent series resistance in junctionless MOSFETs and finally, support the experimental data to extract precisely the carrier mobility in sub-5 nm Si NW MOSFETs

Design and analytical performance of subthreshold characteristics of CSDG MOSFET.

Masters Degree. University of KwaZulu-Natal, Durban.The downscaling of the Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET) devices have been the driving force for Nanotechnology and Very Large-Scale Integration (VLSI) systems. This is affirmed by Moore’s law which states that “The number of transistors placed in an Integrated Circuit (IC) or chip doubles approximately every two years”. The main objectives for the transistor scaling are: to increase functionality, switching speed, packing density and lower the operating power of the ICs. However, the downscaling of the MOSFET device is posed with various challenges such as the threshold roll-off, Drain Induced Barrier Lowing (DIBL), surface scattering, and velocity saturation known as Short Channel Effects (SCEs). To overcome these challenges, a cylindrically structured MOSFET is employed because it increases the switching speed, current flow, packing density, and provides better immunity to SCEs. This thesis proposes a Cylindrical Surrounding Double-Gate (CSDG) MOSFET which is an extended version of Double-Gate (DG) MOSFET and Cylindrical Surrounding-Gate (CSG) MOSFET in terms of form factor and current drive respectively. Furthermore, employing the Evanescent-Mode analysis (EMA) of a two-dimensional (2D) Poisson solution, the performance analysis of the novel CSDG MOSFET is presented. The channel length, radii Silicon film difference, and the oxide thickness are investigated for the CSDG MOSFET at the subthreshold regime. Using the minimum channel potential expression obtained by EMA, the threshold voltage and the subthreshold swing model of the proposed CSDG MOSFET are evaluated and discussed. The device performance is verified with various values of radii Silicon film difference and gate oxide thickness Finally, the low operating power and switching characteristics of the proposed CSDG MOSFET has been employed to design a simple CSDG bridge rectifier circuit for micropower electricity (energy harvester). Similar to the traditional MOSFETs, the switching process of CSDG MOSFET is in two operating modes: switch-ON (conduction of current between the drain and source) or switched-OFF (no conduction of current). However, unlike the traditional diode bridge rectifier which utilizes four diodes for its operation, the CSDG bridge rectifier circuits employs only two CSDGs (n-channel and p- channel) for its operation. This optimizes cost and improves efficiency. Finally, the results from the analyses demonstrate that the proposed CSDG MOSFET is a promising device for nanotechnology and self-micro powered device system application