Scalable Array Transceivers with Wide Frequency Tuning Range for Next Generation Radios

Scalable array transceivers with wide frequency tuning range are attractive for next-generationradios. Key challenges for such radios include generation of LO signals with widefrequency tuning range, scalable synchronization between multiple array unit cells andtolerance to in-band and out-of-band interferers. This thesis presents approaches toaddress these challenges in commercial CMOS technologies.The first part focuses on a series resonant mode-switching VCO architecture thatachieves both state-of-art area and power efficiency with an octave frequency tuningrange from 6.4-14 GHz achieved 186-dB-188-dB Figure-of-Merit (FoM) in 65 nm CMOStechnology. The scalability of this approach towards achieving even larger FTR is alsodemonstrated by a triple-mode 2.2 GHz to 8.7 GHz (119% FTR) CMOS VCO.In the second part a scalable, single-wire coupled-PLL architecture for RF mm-wavearrays is presented. The proposed architecture preserves the simplicity of a daisy-chained LO distribution, compensates for phase offset due to interconnect, and provides phasenoise improvement commensurate to the number of coupled PLLs. Measurements on a28 GHz CMOS prototype demonstrate the feasibility of this scheme.The third part of this thesis presents filtering techniques for in-band blocker suppression.A spatial spectral notch filter design for MIMO digital beam forming arrays is proposedto relax the ADC dynamic range requirement. Orthogonal properties of Walsh functionsincorporated into passive N-path approach enables reconfigurable notches at multiplefrequencies and angles-of-incidence. A 0.3 GHz-1.4 GHz four-element array prototypeimplemented in 65 nm CMOS achieves > 15-dB notch filtering at RF input for twoblockers while causing < 3-dB NF degradation.Finally, a code-domain N-path receiver (RX) is proposed based on pseudo-random(PN) code-modulated LO pulses for simultaneous transmission and reception (STAR)applications. A combination of Walsh-Function and PN sequence is proposed to createcode-domain matched filter at the RF frontend which reflects unknown in-band blockersand rejects known in-band TX self-interference (SI) by using orthogonal codes at RXinput thereby maximizing the SNR of the received signals. The resulting prototype in65 nm is functional from 0.3 GHz-1.4 GHz with 35 dB gain and concurrently receivestwo code-modulated signals. Proposed transmitter (TX) SI mitigation approach resultsin 38.5 dB rejection for -11.8 dBm 1.46 Mb s QPSK modulated SI at RX input. TheRX achieves 23.7 dBm OP1dB for in-band SI, while consuming ∼35 mW and occupies0.31 mm2Keywords: Passive Mixers, dual band, TX self-Interferer, synchronisation, STAR, Code domain N-path receiver, mode switching, notch filter, Phase locked loops, Octave tuning range, CMOS, phase noise, VCO, large-scale 5G mm-wave arrays, resonator, Simultaneous transmit and receive, resonator band-switching, LO distribution, scalable coupled-PLL, N-path passive mixers, MIMO arrays, digital beamforming, CDMA, phased arrays, wide tuning range, Walsh Functio

A Discrete-Time Technique for Linearity Enhancement of Wideband Receivers

A new signal processing technique is introduced to enhance the linearity performance of wideband radio frequency (RF) receivers. The proposed technique combines the advancements in mixer first architectures with a library of binary sequences as local oscillator signals to enable wide instantaneous bandwidth and high linearity for the RF receiver. To do so, N-bit pseudo-random-binary-sequences (PRBS) are used as local oscillator signals. The RF input signal is multiplied with the PRBS at the mixer and then averaged over the full sequence. This in effect reduces the amplitude of the signal and improves the overall linearity of the system. In order to enable full reconstruction of the input signal N channels are used with each employing a shifted version of a PRBS. The effect of the proposed technique on different aspects of the system performance such as noise and linearity is discussed. In addition, the effect of nonidealities stemming from hardware implementation on the overall performance are studied. A prototype integrated circuit (IC) is implemented in 130\,nm CMOS technology to demonstrate the feasibility of the proposed technique. The design procedure of each circuit block is described and simulation results are used to evaluate the performance. The device is fabricated and characterized using a custom data acquisition system. Measurement results show good agreement with the expected values from simulation and analytical analysis. Calibration techniques are introduced to minimize the effect of DC offsets, gain mismatches, and timing skews. Modifications to the implemented CMOS circuit are proposed to enable such calibrations and further enhance the overall performance of the system. The requirements for the precision of calibration techniques are derived and used to find the specifications of circuit block that are designed to enable these techniques. Calibration of DC offsets along with gain mismatches is carried out for the fabricated IC and results are shown. A digitally assisted technique is proposed to enable the calibration of timing skews. In addition, a review of additional implementation shortcomings that can affect the system performance are reviewed. Finally, a conclusion of the dissertation is presented along with potential future work for further enhancement of the system performance

TDRSS telecommunications study. Phase 1: Final report

A parametric analysis of the telecommunications support capability of the Tracking and Data Relay Satellite System (TDRSS) was performed. Emphasis was placed on maximizing support capability provided to the user while minimizing impact on the user spacecraft. This study evaluates the present TDRSS configuration as presented in the TDRSS Definition Phase Study Report, December 1973 to determine potential changes for improving the overall performance. In addition, it provides specifications of the user transponder equipment to be used in the TDRSS

The 30/20 GHz flight experiment system, phase 2. Volume 2: Experiment system description

A detailed technical description of the 30/20 GHz flight experiment system is presented. The overall communication system is described with performance analyses, communication operations, and experiment plans. Hardware descriptions of the payload are given with the tradeoff studies that led to the final design. The spacecraft bus which carries the payload is discussed and its interface with the launch vehicle system is described. Finally, the hardwares and the operations of the terrestrial segment are presented

An analysis of the fundamental constraints on low cost passive radio-frequency identification system design

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2001.Includes bibliographical references (leaves 110-115).Passive radio frequency identification (RFID) systems provide an automatic means to inexpensively, accurately, and flexibly capture information. In combination with the Internet, which allows immediate accessibility and delivery of information, passive RFID systems will allow for increased productivities and efficiencies in every segment of the global supply chain. However, the necessary widespread adoption can only be achieved through improvements in performance - including range, speed, integrity, and compatibility - and in particular, decreases in cost. Designers of systems and standards must fully understand and optimize based on the fundamental constraints on passive RFID systems, which include electromagnetics, communications, regulations, and the limits of physical implementation. In this thesis, I present and analyze these fundamental constraints and their associated trade-offs in view of the important application and configuration dependant specifications.by Tom Ahlkvist Scharfeld.S.M

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Optical quantum random number generation: applications of single-photon event timing

This dissertation is the result of research which, although electrical and computer engineering in nature, also aims to improve the performance of many systems in the field of quantum information. For example, random number generators are used in almost all areas of science, and the initial portion of this work details the theory, design, and characterization of two photon-arrival-time quantum random number generators (QRNGs). After the QRNGs were completed, it was realized that their performance was severely limited both by the maximum detection rate of the single-photon detectors used, and the precision at which the arrival times could be resolved. The single-photon detectors used for both QRNGs are single-photon avalanche photodiodes (SPADs), devices which when operated below their breakdown voltage can create a macroscopic amount of current (an avalanche) in response to a single incident photon. Some of this charge can become trapped in defects or impurities; if this trapped charge is released when the SPAD is active, a secondary ‘false’ detection event, or ‘afterpulse’ can occur. To lower the afterpulse probability to reasonable levels (< 1%), we attempted to reduce the amount of avalanche charge by halting its growth promptly with high-speed electronics, so that defects have a lower probability of becoming populated in the first place. Initial results show reductions in afterpulse probability by up to a factor of 12, corresponding to a ~20% decrease in dead time, a value that could be improved further. We developed an FPGA-based time-to-digital converter system for use specifically with SPADs, achieving a time-bin resolution of 100 ps, with lower dead time and higher maximum detection rate than all currently available detection systems. This further allowed for the creation of a new higher-order SPAD characterization technique, which was identified previously unknown subtleties to SPAD operation. Finally, we developed an ultra-low-latency QRNG, which was used in one of the recent loophole-free demonstrations of quantum nonlocality. The final latency was below 2.5 ns, to our knowledge the lowest latency QRNG to date. Of special interest, however, is our subsequent exploration into the characterization of its bit-probability drift using atomic clock stability techniques. By employing the Allan deviation and implementing precision feedback, the additional frequency drift caused by environmental fluctuations is reduced such that the resulting bit stream can pass cryptographic random number tests for sample sizes up to 5 Gb. This system is currently intended for the NIST random-number beacon, a world-wide trusted source of random bits

Radar Technology

In this book “Radar Technology”, the chapters are divided into four main topic areas: Topic area 1: “Radar Systems” consists of chapters which treat whole radar systems, environment and target functional chain. Topic area 2: “Radar Applications” shows various applications of radar systems, including meteorological radars, ground penetrating radars and glaciology. Topic area 3: “Radar Functional Chain and Signal Processing” describes several aspects of the radar signal processing. From parameter extraction, target detection over tracking and classification technologies. Topic area 4: “Radar Subsystems and Components” consists of design technology of radar subsystem components like antenna design or waveform design

The Telecommunications and Data Acquisition Report

Deep Space Network advanced systems, very large scale integration architecture for decoders, radar interface and control units, microwave time delays, microwave antenna holography, and a radio frequency interference survey are among the topics discussed

Implementation of a VLC HDTV Distribution System for Consumer Premises

A unidirectional, visible light communication (VLC) system intended for the distribution of Digital Video Broadcasting (DVB), high-definition television (HDTV) content to DVB compatible TVs within consumer premises is presented. The system receives off-air HDTV content through a consumer grade DVB-T/T2 terrestrial set-top-box (STB) and re-encodes its Moving Picture Experts Group (MPEG) transport stream (TS) using a pulse position modulation (PPM) scheme called inversion offset PPM (IOPPM). The re-encoded TS is used to intensity modulate (IM) a blue light-emitting diode (LED) operating at a wavelength of 470 nm. Directed line-of-sight (DLOS) transmission is used over a free-space optical (FSO) channel exhibiting a Gaussian impulse response. A direct-detection (DD) receiver is used to detect the transmitted IOPPM stream, which is then decoded to recover the original MPEG TS. A STB supporting a high-definition multimedia interface (HDMI) is used to decode the MPEG TS and enable connectivity to an HD monitor. The system is presented as a complementary or an alternative distribution system to existing Wi-Fi and power-line technologies. VLC connectivity is promoted as a safer, securer, unlicensed and unregulated approach. The system is intended to enable TV manufacturers to reduce costs by, firstly, relocating the TV’s region specific radio frequency (RF) tuner and demodulator blocks to an external STB capable of supporting DVB reception standards, and, secondly, by eliminating all input and output connectors interfaces from the TV. Given the current trend for consumers to wall-mount TVs, the elimination of all connector interfaces, except the power cable, makes mounting simpler and easier. The operation of the final system was verified using real-world, off-air broadcast DVB-T/T2 channels supporting HDTV content. A serial optical transmission at a frequency of 66 MHz was achieved. The system also achieved 60 Mbit/s, error free transmission over a distance of 1.2 m without using error correction techniques. The methodology used to realise the system was a top-down, modular approach. Results were obtained from electrical modelling, simulation and experimental techniques, and using time-domain and FFT based measurements and analysis. The modular approach was adopted to enable design, development and testing of the subsystems independently of the overall system