Methods and Devices for Modifying Active Paths in a K-Delta-1-Sigma Modulator

The invention relates to an improved K-Delta-1-Sigma Modulators (KG1Ss) that achieve multi GHz sampling rates with 90 nm and 45 nm CMOS processes, and that provide the capability to balance performance with power in many applications. The improved KD1Ss activate all paths when high performance is needed (e.g. high bandwidth), and reduce the effective bandwidth by shutting down multiple paths when low performance is required. The improved KD1Ss can adjust the baseband filtering for lower bandwidth, and can provide large savings in power consumption while maintaining the communication link, which is a great advantage in space communications. The improved KD1Ss herein provides a receiver that adjusts to accommodate a higher rate when a packet is received at a low bandwidth, and at a initial lower rate, power is saved by turning off paths in the KD1S Analog to Digital Converter, and where when a higher rate is required, multiple paths are enabled in the KD1S to accommodate the higher band widths

Design of a low power switched-capacitor pipeline analog-to-digital converter

An Analog to Digital Converter (ADC) is a circuit which converts an analog signal into digital signal. Real world is analog, and the data processed by the computer or by other signal processing systems is digital. Therefore, the need for ADCs is obvious. In this thesis, several novel designs used to improve ADCs operation speed and reduce ADC power consumption are proposed. First, a high speed switched source follower (SSF) sample and hold amplifier without feedthrough penalty is implemented and simulated. The SSF sample and hold amplifier can achieve 6 Bit resolution with sampling rate at 10Gs/s. Second, a novel rail-to-rail time domain comparator used in successive approximation register ADC (SAR ADC) is implemented and simulated. The simulation results show that the proposed SAR ADC can only consume 1.3 muW with a 0.7 V power supply. Finally, a prototype pipeline ADC is implemented and fabricated in an IBM 90nm CMOS process. The proposed design is validated using measurement on a fabricated silicon IC, and the proposed 10-bit ADC achieves a peak signal-to-noise- and-distortion-ratio (SNDR) of 47 dB. This SNDR translates to a figure of merit (FOM) of 2.6N/conversion-step with a 1.2 V power supply

Parallel Delta-Sigma Modulator-Based Digital Predistortion of Wideband RF Power Amplifiers

In this article, we propose a new robust and highly efficient digital predistortion (DPD) concept for the linearization of wideband RF power amplifiers (PAs). The proposed approach is based on the combination of a parallelized delta-sigma modulator (DSM) and a forward model of the PA. This concept applies multi-rate techniques on a DSM that incorporates the forward PA model in its feedback loop to perform the required signal predistortion. Such a technique eliminates the need of reverse modeling and its associated problems. The multi-rate approach relaxes enormously the clock speed requirement of the DPD, which allows handling high signal bandwidths at feasible sampling rates. Moreover, enhanced performance can be achieved without the need of increasing the order of the modulator which reduces the sensitivity of the system to gain variations and phase distortions caused by the nonlinear PA characteristics. Three time-interleaved parallel DPD (P-DPD) variants are described and introduced, all of them have been shown to offer increased accuracy, and consequently better linearization performance compared to the DSM-based DPD state-of-the-art. The proposed architectures are tested and assessed using extensive real-world RF measurements at the 3.6 GHz band utilizing wideband 100 MHz 5G New Radio (NR) transmit waveforms, evidencing excellent transmit signal quality.publishedVersionPeer reviewe

Design, Fabrication and Testing of Monolithic Low-Power Passive Sigma-Delta Analog-to-Digital Converters

Analog-to-digital converters are critically important in electronic systems. The difficulty in meeting high performance parameters increases as integrated circuit design process technologies advance into the deep nanometer region. Sigma-delta analog-todigital converters are an attractive option to fulfill many data converter requirements. These data converters offer high performance while relaxing requirements on the precision of components within an integrated circuit. Despite this, the active integrators found within sigma-delta analog-to-digital converters present two main challenges. These challenges are the power consumption of the active amplifier and achieving gain-bandwidth necessary for sigma-delta data converters in deep nanometer process technologies. Both of these challenges can be resolved through the replacement of active integrators with passive integrators at the expense of resolution. Three passive sigma-delta topologies were examined and characterized in detail. Two of these topologies were first-order and second-order noise shaping topologies. A new passive topology was developed which was determined to be optimal in resolution compared to the two traditional designs. This topology exhibits a first-order signal transfer function and a second-order noise transfer function. A method for increasing resolution of passive sigma-delta data converters despite inherent performance constraints was developed. Three example circuits were designed, fabricated and tested using On Semiconductor’s C5 500 nanometer CMOS process. These designs were optimized for low power and utilized memory sense amplifiers as quantizing elements. The first circuit, using passive lumped on-chip elements for the noise shaping network achieved a power consumption of 100 micro-watts and an effective resolution of 8-bits. The second circuit replaced the lumped components with switched-capacitor elements and achieved a power consumption of 6.75 micro-watts and an effective resolution of 9.3 bits. The third circuit was designed as a case study for the application of the proposed topology to “K-delta-1- sigma” modulators. This circuit achieved a power consumption of 10 milli-watts and an effective resolution of 8.5 bits

Novel structures for high-speed delta-sigma data converters

As CMOS processes keep scaling down devices, the maximum operating frequencies of CMOS devices increase, and hence circuits can process very wide band signals. Moreover, the small physical dimensions of transistors allow the placing of many more blocks into a single chip, including highly accurate analog blocks and complicated digital blocks, which can process audio to communication data. Nowadays, wideband and low-power data converter is mandatory for mobile applications which need a bridge between analog and digital blocks. In this dissertation, low-power and wideband techniques are proposed. An embedded-adder quantizer with dynamic preamplifier is proposed to achieve power-efficient operation. Various double-sampling schemes are studied, and novel schemes are presented to achieve wideband operation without noise folding effect. To reduce timing delay and idle tones, a high speed DEM which alternates two sets of comparator references is proposed. Multi-cell architecture is studied to insure higher performance when the number of modulators increases. 0.18 um double-poly/4-metal CMOS process was used to implement a prototype IC. 20 MHz signal bandwidth was achieved with a 320 MHz sampling clock. The peak SNDR was 63 dB. The figure-of-merit FoM = P/(2*BW*2[superscript ENOB]) was 0.35 pJ/conversion, with a 16 mW power consumption. Measurement results show that the proposed design ideas are useful for low-power and wideband delta-sigma modulators which have low OSR. A second-order noise-coupled modulator with an embedded-zero optimization was proposed to reduce power consumption by eliminating some of the integrators. This architecture makes easier the implementation of the small feedback capacitors for high OSR modulators

Wideband CMOS Data Converters for Linear and Efficient mmWave Transmitters

With continuously increasing demands for wireless connectivity, higher\ua0carrier frequencies and wider bandwidths are explored. To overcome a limited transmit power at these higher carrier frequencies, multiple\ua0input multiple output (MIMO) systems, with a large number of transmitters\ua0and antennas, are used to direct the transmitted power towards\ua0the user. With a large transmitter count, each individual transmitter\ua0needs to be small and allow for tight integration with digital circuits. In\ua0addition, modern communication standards require linear transmitters,\ua0making linearity an important factor in the transmitter design.In this thesis, radio frequency digital-to-analog converter (RF-DAC)-based transmitters are explored. They shift the transition from digital\ua0to analog closer to the antennas, performing both digital-to-analog\ua0conversion and up-conversion in a single block. To reduce the need for\ua0computationally costly digital predistortion (DPD), a linear and wellbehaved\ua0RF-DAC transfer characteristic is desirable. The combination\ua0of non-overlapping local oscillator (LO) signals and an expanding segmented\ua0non-linear RF-DAC scaling is evaluated as a way to linearize\ua0the transmitter. This linearization concept has been studied both for\ua0the linearization of the RF-DAC itself and for the joint linearization of\ua0the cascaded RF-DAC-based modulator and power amplifier (PA) combination.\ua0To adapt the linearization, observation receivers are needed.\ua0In these, high-speed analog-to-digital converters (ADCs) have a central\ua0role. A high-speed ADC has been designed and evaluated to understand\ua0how concepts used to increase the sample rate affect the dynamic performance

Concurrent Dual Band Radio-over-Fiber Transmission Using 1-bit Envelope Delta-Sigma Modulation

With the growing demand for bandwidth and transmission speed, mobile communication network designs must stay adaptable, efficient and cost-effective. A key integration has been Radio-over-Fiber (RoF) transmission systems that provide a cheaper option and low loss for high frequency signal transfer. For the optical transmitter, delta-sigma modulation (DSM) can be a beneficial addition. The partnership simplifies the Digital-Radio-over-Fiber setup by removing the need for additional converters and prompts adjustments based on system need. Main factors in delta-sigma modulators are the amount of quantization bits and the order of the modulator. Changing quantization bits to a single bit allows the system to use less processing bandwidth and less error experienced from optical transmission. High order structures provide more noise shaping to shift noise away from the band of interest. Still, such setups are prone to linearity problems due to clock jitter from multiple feedback loops. Different adaptations of delta-sigma modulation have been designed to combat the problems, but a key standout is the implementation of an envelope delta-sigma modulation (EDSM). Envelope delta-sigma modulation’s separate processing of envelope and phase delivers time alignment and noise shaping counter the negative implications from high order DSMs. Combining envelope delta-sigma modulation with RoF transmission is an attractive option, but research has yet to delve into carrier aggregation with these setups. This thesis explores concurrent dual band 64-QAM 20 MHz LTE Radio-over-Fiber using 1-bit envelope delta-sigma modulation. It expands transmitter functionality by concurrent signal integration. Inside the EDSM is a 4th order bandpass delta-sigma modulator custom tailored one of two carrier frequencies. The two frequencies come from two different LTE bands to show interband compatibility. The carrier frequencies are 2.112 GHz from LTE band 1 and 2.64 GHz from LTE band 7. Simulation and experimental results confirm the functionality of the proposed envelope delta-sigma modulation RoF system in single and dual band for LTE standards (error vector magnitude < 8%). Experimental results confirm that EDSM is more resilient to RoF transmission than BP-DSM. However, the EVM values for BP-DSM are better for carrier aggregated transmission

High Capacity Fiber-Connected Wireless MIMO Communication

There will be more and more users while beyond-5G (B5G) and 6G bring more wireless applications. Current cellular communication networks assign specific serving boundaries for each radio, which becomes a limitation when too many users work with one radio simultaneously. By physically distributing radios. user’s service can be more uniform. Radio-over-fiber is a promising enabling technology for distributed antenna systems.To have several tens of Gbit/s data rate, we need to apply millimeter-wave (mm-wave) frequency band in radio-over-fiber (RoF). However, mm-wave signals have weak penetration and high propagation loss. Hence, beamforming and/or multiple-input-multiple-output (MIMO) technology become necessary for mm-wave RoF to overcome those drawbacks.This thesis introduces an automatic distributed MIMO (D-MIMO) testbed with a statistical MIMO capacity analysis for an indoor use case. Raytracing-based simulations also predicts the indoor case to make a comparison. The statistical MIMO capacity analysis shows that D-MIMO has a higher and more uniform capacity than co-located MIMO (C-MIMO) in measurements and simulations.Next, a mm-wave sigma-delta-over-fiber (SDoF) link architecture is proposed for MIMO applications. In the implementation of this link, a QSFP28 fiber link connects a central unit with a remote radio unit with four bandpass sigma-delta-modulation (BPSDM) bitstreams. The remote radio unit generates four mm-wave signals from four BPSDM signals and feeds a linear array antenna. The measurement characterizes the remote radio head at each stage and concludes that this proposed link can reach 800 Msym/s data rate with -0.5 dBm output bandpower.Furthermore, the proposed link is demonstrated with digital beamforming and multi-user MIMO (MU-MIMO) functionalities. The digital beamforming function reaches 700 Msym/s with -25 dB error vector magnitude (EVM) results by improving the received bandpower in comparison to (single-input-single-output) SISO results. The MU-MIMO function serves two independent users at 500 Msym/s symbol rate and satisfies 3GPP requirements at 1 m over-the-air distance.In conclusion, this thesis proves that D-MIMO has a higher and more uniform capacity than C-MIMO by statistical analysis from measurements and simulations. The proposed novel mm-wave SDoF link can pave the way for future D-MIMO applications