The truth about 2-level transition elimination in bang-bang PAM-4 CDRs

Reception of 4-level pulse amplitude modulation (PAM-4) requires a clock and data recovery (CDR) circuit, typically implemented by a PLL-like structure. An essential block in such a CDR is the phase detector which should detect whether the recovered clock leads or lags the incoming data edges. In typical implementations an incoming data edge is detected by sensing whether the incoming waveform crosses a data threshold level. However, there is some ambiguity in detecting the incoming data edge because PAM-4 modulation has 3 thresholds. If the waveform crosses multiple threshold levels, the level crossings will occur at different time instants due to the finite rise/fall time of the incoming waveform. In this work, we first analyze qualitatively and quantitatively CDR systems that use one threshold for phase adjustment. Here, eliminating the 2-level transitions decreases the amount of jitter injected by the phase detector. However, the available transitions for phase adjustment are also reduced, which lowers the CDR's robustness. Secondly, for CDR systems using three thresholds, a combination of two techniques: majority voting and elimination of 2-level transitions is investigated. We prove that in this case, the elimination of 2-level transitions is not needed and even gives a worse performance when implemented

High Performance Optical Transmitter Ffr Next Generation Supercomputing and Data Communication

High speed optical interconnects consuming low power at affordable prices are always a major area of research focus. For the backbone network infrastructure, the need for more bandwidth driven by streaming video and other data intensive applications such as cloud computing has been steadily pushing the link speed to the 40Gb/s and 100Gb/s domain. However, high power consumption, low link density and high cost seriously prevent traditional optical transceiver from being the next generation of optical link technology. For short reach communications, such as interconnects in supercomputers, the issues related to the existing electrical links become a major bottleneck for the next generation of High Performance Computing (HPC). Both applications are seeking for an innovative solution of optical links to tackle those current issues. In order to target the next generation of supercomputers and data communication, we propose to develop a high performance optical transmitter by utilizing CISCO Systems®\u27s proprietary CMOS photonic technology. The research seeks to achieve the following outcomes: 1. Reduction of power consumption due to optical interconnects to less than 5pJ/bit without the need for Ring Resonators or DWDM and less than 300fJ/bit for short distance data bus applications. 2. Enable the increase in performance (computing speed) from Peta-Flop to Exa-Flops without the proportional increase in cost or power consumption that would be prohibitive to next generation system architectures by means of increasing the maximum data transmission rate over a single fiber. 3. Explore advanced modulation schemes such as PAM-16 (Pulse-Amplitude-Modulation with 16 levels) to increase the spectrum efficiency while keeping the same or less power figure. This research will focus on the improvement of both the electrical IC and optical IC for the optical transmitter. An accurate circuit model of the optical device is created to speed up the performance optimization and enable co-simulation of electrical driver. Circuit architectures are chosen to minimize the power consumption without sacrificing the speed and noise immunity. As a result, a silicon photonic based optical transmitter employing 1V supply, featuring 20Gb/s data rate is fabricated. The system consists of an electrical driver in 40nm CMOS and an optical MZI modulator with an RF length of less than 0.5mm in 0.13&mu m SOI CMOS. Two modulation schemes are successfully demonstrated: On-Off Keying (OOK) and Pulse-Amplitude-Modulation-N (PAM-N N=4, 16). Both versions demonstrate signal integrity, interface density, and scalability that fit into the next generation data communication and exa-scale computing. Modulation power at 20Gb/s data rate for OOK and PAM-16 of 4pJ/bit and 0.25pJ/bit are achieved for the first time of an MZI type optical modulator, respectively

Digital Signal Processing on FPGA for Short-Range Optical Communications Systems over Plastic Optical Fiber

Nowadays bandwidth requirements are increasing vertiginously. As new ways and concepts of how to share information emerge, new ways of how to access the web enter the market. Computers and mobile devices are only the beginning, the spectrum of web products and services such as IPTV, VoIP, on-line gaming, etc has been augmented by the possibility to share, store data, interact and work on the Cloud. The rush for bandwidth has led researchers from all over the world to enquire themselves on how to achieve higher data rates, and it is thanks to their efforts, that both long-haul and short-range communications systems have experienced a huge development during the last few years. However, as the demand for higher information throughput increases traditional short-range solutions reach their lim- its. As a result, optical solutions are now migrating from long-haul to short-range communication systems. As part of this trend, plastic optical fiber (POF) systems have arisen as promising candidates for applications where traditional glass optical fibers (GOF) are unsuitable. POF systems feature a series of characteristics that make them very suitable for the market requirements. More in detail, these systems are low cost, robust, easy to handle and to install, flexible and yet tolerant to bendings. Nonetheless, these features come at the expense of a considerable higher bandwidth limitation when compared to GOF systems. This thesis is aimed to the investigate the use of digital signal processing (DSP) algorithms to overcome the bandwidth limitation in short-range optical communications system based on POF. In particular, this dissertation presents the design and development of DSP algorithms on field programmable gate arrays (FPGAs) with the ultimate purpose of implementing a fully engineered 1Gbit/s Ethernet Media Converter capable of establishing data links over 50+ meters of PMMA-SI POF using an RC-LED as transmitte

DESIGN AND CHARACTERIZATION OF LOW-POWER LOW-NOISE ALLDIGITAL SERIAL LINK FOR POINT-TO-POINT COMMUNICATION IN SOC

The fully-digital implementation of serial links has recently emerged as a viable alternative to their classical analogue counterpart. Indeed, reducing the analogue content in favour of expanding the digital content becomes more attractive due to the ability to achieve less power consumption, less sensitivity to the noise and better scalability across multiple technologies and platforms with inconsiderable modifications. In addition, describing the circuit in hardware description languages gives it a high flexibility to program all design parameters in a very short time compared with the analogue designs which need to be re-designed at transistor level for any parameter change. This can radically reduce cost and time-to-market by saving a significant amount of development time. However, beside these considerable advantages, the fully-digital architecture poses several design challenges

Deterministic Jitter in Broadband Communication

The past decade has witnessed a drastic change in the design of high-speed serial links. While Silicon fabrication technology has produced smaller, faster transistors, transmission line interconnects between chips and through backplanes have not substantially improved and have a practical bandwidth of around 3GHz. As serial link speeds increase, new techniques must be introduced to overcome the bandwidth limitation and maintain digital signal integrity. This thesis studies timing issues pertaining to bandwidth-limited interconnects. Jitter is defined as the timing uncertainty at a threshold used to detect the digital signal. Reliable digital communication requires minimizing jitter. The analysis and modeling presented here focuses on two types of deterministic jitter. First, dispersion of the digital signal in a bandwidth-limited channel creates data-dependent jitter. Our analysis links data sequences to unique timing deviations through the channel response and is shown for general linear time-invariant systems. A Markov model is constructed to study the impact of jitter on the operation of the serial link and provide insight in circuit performance. Second, an analysis of bounded-uncorrected jitter resulting from crosstalk induced in parallel serial links is presented. Timing equalization is introduced to improve the signal integrity of high-speed links. The analysis of deterministic jitter leads to novel techniques for compensating the timing ambiguity in the received data. Data-dependent jitter equalization is discussed at both the receiver, where it complements the operation of clock and data recovery circuits, and as a phase pre-emphasis technique. Crosstalk-induced, bounded-uncorrected jitter can also be compensated. By detecting electromagnetic modes between neighboring serial links, a transmitter or receiver anticipates the timing deviation that has occurred along the transmission line. Finally, we discuss a new circuit technique for submillimeter integrated circuits. Demands of wireless communication and the high speed of Silicon Germanium transistors provide opportunities for unique radio architectures for submillimeter integrated circuits. Scalable, fully-integrated phased arrays control a radiated beam pattern electronically through tiling multiple chips. Coupled-oscillator arrays are used for the first time to subharmonically injection-lock across a chip or between multiple chips to provide phase coherence across an array.</p

데이터 전송로 확장성과 루프 선형성을 향상시킨 다중채널 수신기들에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 2. 정덕균.Two types of serial data communication receivers that adopt a multichannel architecture for a high aggregate I/O bandwidth are presented. Two techniques for collaboration and sharing among channels are proposed to enhance the loop-linearity and channel-expandability of multichannel receivers, respectively. The first proposed receiver employs a collaborative timing scheme recovery which relies on the sharing of all outputs of phase detectors (PDs) among channels to extract common information about the timing and multilevel signaling architecture of PAM-4. The shared timing information is processed by a common global loop filter and is used to update the phase of the voltage-controlled oscillator with better rejection of per-channel noise. In addition to collaborative timing recovery, a simple linearization technique for binary PDs is proposed. The technique realizes a high-rate oversampling PD while the hardware cost is equivalent to that of a conventional 2x-oversampling clock and data recovery. The first receiver exploiting the collaborative timing recovery architecture is designed using 45-nm CMOS technology. A single data lane occupies a 0.195-mm2 area and consumes a relatively low 17.9 mW at 6 Gb/s at 1.0V. Therefore, the power efficiency is 2.98 mW/Gb/s. The simulated jitter is about 0.034 UI RMS given an input jitter value of 0.03 UI RMS, while the relatively constant loop bandwidth with the PD linearization technique is about 7.3-MHz regardless of the data-stream noise. Unlike the first receiver, the second proposed multichannel receiver was designed to reduce the hardware complexity of each lane. The receiver employs shared calibration logic among channels and yet achieves superior channel expandability with slim data lanes. A shared global calibration control, which is used in a forwarded clock receiver based on a multiphase delay-locked loop, accomplishes skew calibration, equalizer adaptation, and the phase lock of all channels during a calibration period, resulting in reduced hardware overhead and less area required by each data lane. The second forwarded clock receiver is designed in 90-nm CMOS technology. It achieves error-free eye openings of more than 0.5 UI across 9− 28 inch Nelco 4000-6 microstrips at 4− 7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only 0.152 mm2 and consumes 69.8 mW, while the rest of the receiver occupies 0.297 mm2 and consumes 56 mW at a data rate of 7 Gb/s and a supply voltage of 1.35 V.1. Introduction 1 1.1 Motivations 1.2 Thesis Organization 2. Previous Receivers for Serial-Data Communications 2.1 Classification of the Links 2.2 Clocking architecture of transceivers 2.3 Components of receiver 2.3.1 Channel loss 2.3.2 Equalizer 2.3.3 Clock and data recovery circuit 2.3.3.1. Basic architecture 2.3.3.2. Phase detector 2.3.3.2.1. Linear phase detector 2.3.3.2.2. Binary phase detector 2.3.3.3. Frequency detector 2.3.3.4. Charge pump 2.3.3.5. Voltage controlled oscillator and delay-line 2.3.4 Loop dynamics of PLL 2.3.5 Loop dynamics of DLL 3. The Proposed PLL-Based Receiver with Loop Linearization Technique 3.1 Introduction 3.2 Motivation 3.3 Overview of binary phase detection 3.4 The proposed BBPD linearization technique 3.4.1 Architecture of the proposed PLL-based receiver 3.4.2 Linearization technique of binary phase detection 3.4.3 Rotational pattern of sampling phase offset 3.5 PD gain analysis and optimization 3.6 Loop Dynamics of the 2nd-order CDR 3.7 Verification with the time-accurate behavioral simulation 3.8 Summary 4. The Proposed DLL-Based Receiver with Forwarded-Clock 4.1 Introduction 4.2 Motivation 4.3 Design consideration 4.4 Architecture of the proposed forwarded-clock receiver 4.5 Circuit description 4.5.1 Analog multi-phase DLL 4.5.2 Dual-input interpolating deley cells 4.5.3 Dedicated half-rate data samplers 4.5.4 Cherry-Hooper continuous-time linear equalizer 4.5.5 Equalizer adaptation and phase-lock scheme 4.6 Measurement results 5. Conclusion 6. BibliographyDocto

Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

An Energy-Efficient Reconfigurable Mobile Memory Interface for Computing Systems

The critical need for higher power efficiency and bandwidth transceiver design has significantly increased as mobile devices, such as smart phones, laptops, tablets, and ultra-portable personal digital assistants continue to be constructed using heterogeneous intellectual properties such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors, dynamic random-access memories (DRAMs), sensors, and graphics/image processing units and to have enhanced graphic computing and video processing capabilities. However, the current mobile interface technologies which support CPU to memory communication (e.g. baseband-only signaling) have critical limitations, particularly super-linear energy consumption, limited bandwidth, and non-reconfigurable data access. As a consequence, there is a critical need to improve both energy efficiency and bandwidth for future mobile devices.;The primary goal of this study is to design an energy-efficient reconfigurable mobile memory interface for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed energy efficient mobile memory interface which utilizes an advanced base-band (BB) signaling and a RF-band signaling is capable of simultaneous bi-directional communication and reconfigurable data access. It also increases power efficiency and bandwidth between mobile CPUs and memory subsystems on a single-ended shared transmission line. Moreover, due to multiple data communication on a single-ended shared transmission line, the number of transmission lines between mobile CPU and memories is considerably reduced, resulting in significant technological innovations, (e.g. more compact devices and low cost packaging to mobile communication interface) and establishing the principles and feasibility of technologies for future mobile system applications. The operation and performance of the proposed transceiver are analyzed and its circuit implementation is discussed in details. A chip prototype of the transceiver was implemented in a 65nm CMOS process technology. In the measurement, the transceiver exhibits higher aggregate data throughput and better energy efficiency compared to prior works

Highly digital power efficient techniques for serial links

Low power, high speed serial transceivers are employed in a wide range of applications ranging from chip-to-chip, backplane, and optical interconnects. Apart from being capable of handling a wide range of data rates, the transceivers should have low power consumption (mW/Gbps) and be fully integrated. This work discusses enabling techniques to implement such transceivers. Specifically, three designs: (1) a 0.5-4 Gbps serial link which uses current recycling to reduce power dissipation and (2) a 0.5-2.5 Gbps reference-less clock and data recovery circuit which uses a novel frequency detector to achieve unlimited acquisition range and (3) a 2-4 Gbps low power receiver architecture capable of resolving multiple signalling formats with a simplified XOR based phase rotating PLL will be presented. All the three circuit topologies are highly digital and aim to address the requirements of wide operating range, low power dissipation while being fully integrated. Measured results obtained from the prototypes illustrate the effectiveness of the proposed design techniques

Reducing jitter utilising adaptive pre-emphasis FIR filter for high speed serial links

Jitter requirements have become more stringent with higher speed serial communication links. Reducing jitter, with the main focus on reducing data dependant jitter (DDJ), is presented by employing adaptive finite impulse response (FIR) filter pre-emphasis. The adaptive FIR pre-emphasis is implemented in the IBM 7WL 0.18 µm SiGe BiCMOS process. SiGe heterojunction bipolar transistors (HBTs) provide high bandwidth, low noise devices which could reduce the total system jitter. The trade-offs between utilising metal oxide semiconductor (MOS) current mode logic (CML) and SiGe bipolar CML are also discussed in comparison with a very high fT (IBM 8HP process with fT = 200 GHz) process. A reduction in total system jitter can be achieved by keeping the sub-components of the system jitter constant while optimising the DDJ. High speed CML circuits have been employed to allow data rates in excess of 5 Gb/s to be transmitted whilst still maintaining an internal voltage swing of at least 300 mV. This allows the final FIR filter adaptation scheme to minimise the DDJ within 12.5 % of a unit interval, at a data rate of 5 Gb/s implementing 6 FIR pre-emphasis filter taps, for a worst case copper backplane channel (30" FR-4 channel). The implemented integrated circuit (IC) designed as part of the verification process takes up less than 1 mm2 of silicon real estate. In this dissertation, SPICE simulation results are presented, as well as the novel IC implementation of the proposed FIR filter adaptation technique as part of the hypothesis verification procedure. The implemented transmitter and receiver were tested for functionality, and showed the successful functional behaviour of all the implemented CML gates associated with the first filter tap. However, due to the slow charge and discharge rate of the pulse generation circuit in both the transmitter and receiver, only the main operational state of the transmitter could be experimentally validated. As a result of the adaptation scheme implemented, the contribution in this research lies in that a designer utilising such an IC can optimise the DDJ, reducing the total system jitter, and hence increasing the data fidelity with minimal effort.Dissertation (MEng)--University of Pretoria, 2011.Electrical, Electronic and Computer Engineeringunrestricte