Slew-rate enhancement and trojan state avoiding for fully-differential operational amplifier

Operational amplifiers are fundamental building blocks in modern analog and mixed-signal systems such as data converters, switched-capacitor circuits, and filters. The fully-differential structure is extensively used in these applications because of its improved dynamic performance with respect to such aspects as signal-to-noise ratio (SNR) and total harmonic distortion (THD) when compared to its single-ended counterpart. In some of these applications, the fully-differential amplifier is required to have fast transient settling time without slew-rate limitations. Power consumption also must be taken into consideration because low power consumption can significantly reduce a battery\u27s weight and size, and extend its life-time. A Class A amplifier is a difficult configuration in which to conciliate all these requirements, since its fixed bias current can limit its maximum output current. To simultaneously meet both slew-rate and power consumption requirements, several slew-rate enhancement (SRE) techniques have been proposed in the literature, but all of them are either incompatible with the low voltage operation or exhibit either degradation in linearity or increase in circuit complexity. This thesis presents a simple SRE technique, efficient in both power and area usage, improve the slew rate while overcoming the drawbacks of state-of-the-art SRE techniques. In this work, several existing SRE techniques are discussed, and their advantages and disadvantages are identified. The proposed SRE technique is based on excess transient detection and feedback. A transient signal can be detected at the internal nodes of amplifier. Once the detected transient signal is found to be larger than a pre-defined turn-on value, the excess transient signal can be instantaneously amplified to turn on a dynamic current source and feed it back to the amplifier for current boosting. This pre-defined turn-on voltage results in a SRE circuit being solidly off during quiescent state. Small-signal performance and linearity of the original amplifier can be thus well preserved. Thanks to this excess transient feedback concept, the implementation is much simpler than that of previously reported methods, and the static power overhead is also very small. Using the proposed SRE method, a fully-differential folded-cascode two-stage op-amp has been designed and fabricated using IBM 130nm process. This amplifier is designed to validate the proposed method of improving an amplifier\u27s input-stage slew-rate. If the tail current doubles during slewing, the simulation result indicates that, at all corners, with temperature from 0°C to 60°C the average slew-rate can be enhanced by a factor of 2.6 and the 1% settling time after a large input step is reduced by 30% compared to the vales without using SRE. Any further increment in the tail transient current can further increase the internal slew rate and eventually make it equal to the output-stage slew-rate. It is well-known that self-stabilized circuits, such as current, voltage and frequency references, are vulnerable to a problem of multiple operating points; this is also known as the start-up problem. An op-amp can suffer from the same problem when performance enhancement feedback is being used. In particular, a slew rate enhancement circuit (SRE) can be used to provide performance enhancement in low-power high-speed op-amp design. For such circuits, a systematic method for detecting and removal of Trojan states is presented. Using a design example and simulation results, it is demonstrated that the proposed method can effectively remove a Trojan state in an op-amp without degrading the improved slew-rate

Class-D Audio Amplifier using Sigma-Delta (ΣΔ) Modulator

Pulse width modulation and pulse density modulation are deemed to be main modulation techniques, even PDM could not emulate PWM, in terms of, basically, simplicity. PDM bitstream is encoded through sigma-delta modulation. Since sigma-delta modulation, compared to PWM, needs very high switching frequency and more complicated materials to compose circuits, it’s more difficult to design one. In this article we design a low-power class-D audio amplifier circuit where the analog signal is encoded into pulse density modulation (PDM) using a first-order sigma-delta (ΣΔ) modulator. The designed circuit is built using Orcad-PSpice and results are analyzed with Matlab. A second-order integrator, a voltage divider as a feedback loop are used to mitigate basically, THD and get high efficiency. The audio signal is passed to the EM speaker through a Butterworth low-pass filter. A low THD of less than 0.2 % is obtained comparing to similar circuits in the literature and a high efficiency of 92 % is achieved.

Design and Analysis of a Dual Supply Class H Audio Amplifier

abstract: Efficiency of components is an ever increasing area of importance to portable applications, where a finite battery means finite operating time. Higher efficiency devices need to be designed that don't compromise on the performance that the consumer has come to expect. Class D amplifiers deliver on the goal of increased efficiency, but at the cost of distortion. Class AB amplifiers have low efficiency, but high linearity. By modulating the supply voltage of a Class AB amplifier to make a Class H amplifier, the efficiency can increase while still maintaining the Class AB level of linearity. A 92dB Power Supply Rejection Ratio (PSRR) Class AB amplifier and a Class H amplifier were designed in a 0.24um process for portable audio applications. Using a multiphase buck converter increased the efficiency of the Class H amplifier while still maintaining a fast response time to respond to audio frequencies. The Class H amplifier had an efficiency above the Class AB amplifier by 5-7% from 5-30mW of output power without affecting the total harmonic distortion (THD) at the design specifications. The Class H amplifier design met all design specifications and showed performance comparable to the designed Class AB amplifier across 1kHz-20kHz and 0.01mW-30mW. The Class H design was able to output 30mW into 16Ohms without any increase in THD. This design shows that Class H amplifiers merit more research into their potential for increasing efficiency of audio amplifiers and that even simple designs can give significant increases in efficiency without compromising linearity.Dissertation/ThesisM.S. Electrical Engineering 201

High linearity analog and mixed-signal integrated circuit design

Linearity is one of the most important specifications in electrical circuits.;In Chapter 1, a ladder-based transconductance networks has been adopted first time to build a low distortion analog filters for low frequency applications. This new technique eliminated the limitation of the application with the traditional passive resistors for low frequency applications. Based on the understanding of this relationship, a strategy for designing high linear analog continuous-time filters has been developed. According to our strategy, a prototype analog integrated filter has been designed and fabricated with AMI05 0.5 um standard CMOS process. Experimental results proved this technique has the ability to provide excellent linearity with very limited active area.;In Chapter 2, the relationships between the transconductance networks and major circuit specifications have been explored. The analysis reveals the trade off between the silicon area saved by the transconductance networks and the some other important specifications such as linearity, noise level and the process variations of the overall circuit. Experimental results of discrete component circuit matched very well with our analytical outcomes to predict the change of linearity and noise performance associated with different transconductance networks.;The Chapter 3 contains the analysis and mathematical proves of the optimum passive area allocations for several most popular analog active filters. Because the total area is now manageable by the technique introduced in the Chapter 1, the further reduce of the total area will be very important and useful for efficient utilizing the silicon area, especially with the today\u27s fast growing area efficiency of the highly density digital circuits. This study presents the mathematical conclusion that the minimum passive area will be achieved with the equalized resistor and capacitor.;In the Chapter 4, a well recognized and highly honored current division circuit has been studied. Although it was claimed to be inherently linear and there are over 60 published works reported with high linearity based on this technique, our study discovered that this current division circuit can achieve, if proper circuit condition being managed, very limited linearity and all the experimental verified performance actually based on more general circuit principle. Besides its limitation, however, we invented a novel current division digital to analog converter (DAC) based on this technique. Benefiting from the simple circuit structure and moderate good linearity, a prototype 8-bit DAC was designed in TSMC018 0.2 um CMOS process and the post layout simulations exhibited the good linearity with very low power consumption and extreme small active area.;As the part of study of the output stage for the current division DAC discussed in the Chapter 4, a current mirror is expected to amplify the output current to drive the low resistive load. The strategy of achieving the optimum bandwidth of the cascode current mirror with fixed total current gain is discussed in the Chapter 5.;Improving the linearity of pipeline ADC has been the hottest and hardest topic in solid-state circuit community for decade. In the Chapter 6, a comprehensive study focus on the existing calibration algorithms for pipeline ADCs is presented. The benefits and limitations of different calibration algorithms have been discussed. Based on the understanding of those reported works, a new model-based calibration is delivered. The simulation results demonstrate that the model-based algorithms are vulnerable to the model accuracy and this weakness is very hard to be removed. From there, we predict the future developments of calibration algorithms that can break the linearity limitations for pipelined ADC. (Abstract shortened by UMI.

Novel techniques for the design and practical realization of switched-capacitor circuits in deep-submicron CMOS technologies

Dissertação apresentada para obtenção do Grau de Doutor em Engenharia Electrotécnica e de Computadores pela Universidade Nova de Lisboa, Faculdade de Ciências e TecnologiaSwitches presenting high linearity are more and more required in switched-capacitor circuits,namely in 12 to 16 bits resolution analog-to-digital converters. The CMOS technology evolves continuously towards lower supply voltages and, simultaneously, new design techniques are necessary to fulfill the realization of switches exhibiting a high dynamic range and a distortion compatible with referred resolutions. Moreover, with the continuously downing of the sizes, the physic constraints of the technology must be considered to avoid the excessive stress of the devices when relatively high voltages are applied to the gates. New switch-linearization techniques, with high reliability, must be necessarily developed and demonstrated in CMOS integrated circuits. Also, the research of new structures of circuits with switched-capacitor is permanent. Simplified and efficient structures are mandatory, adequate to the new demands emerging from the proliferation of portable equipments, necessarily with low energy consumption while assuring high performance and multiple functions. The work reported in this Thesis comprises these two areas. The behavior of the switches under these new constraints is analyzed, being a new and original solution proposed, in order to maintain the performance. Also, proposals for the application of simpler clock and control schemes are presented, and for the use of open-loop structures and amplifiers with localfeedback. The results, obtained in laboratory or by simulation, assess the feasibility of the presented proposals

1 V CMOS subthreshold log domain PDM

A new CMOS circuit strategy for very low-voltage Pulse-Duration Modulators (PDM) is proposed. Optimization of voltage supply scaling below the sum of threshold voltages is based on Instantaneous Log Companding processing through the MOSFET operating in weak inversion. A 1 V VLSI PDM circuit for very low-voltage audio applications such as Hearing Aids is presented, showing good agreement between simulated and experimental data.Comisión Interministerial de Ciencia y Tecnología TIC97-1159, TIC99-1084European Union 2306

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

Sigma-delta class D audio power amplifier in CMOS technology

Master'sMASTER OF ENGINEERIN