Testing high resolution SD ADC’s by using the noise transfer function

A new solution to improve the testability of high resolution SD Analogue to Digital Converters (SD ADC’s) using the quantizer input as test node is described. The theoretical basis for the technique is discussed and results from high level simulations for a 16 bit, 4th order, audio ADC are presented. The analysis demonstrates the potential to reduce the computational effort associated with test response analysis versus conventional techniques

Programmable CMOS Analog-to-Digital Converter Design and Testability

In this work, a programmable second order oversampling CMOS delta-sigma analog-to-digital converter (ADC) design in 0.5µm n-well CMOS processes is presented for integration in sensor nodes for wireless sensor networks. The digital cascaded integrator comb (CIC) decimation filter is designed to operate at three different oversampling ratios of 16, 32 and 64 to give three different resolutions of 9, 12 and 14 bits, respectively which impact the power consumption of the sensor nodes. Since the major part of power consumed in the CIC decimator is by the integrators, an alternate design is introduced by inserting coder circuits and reusing the same integrators for different resolutions and oversampling ratios to reduce power consumption. The measured peak signal-to-noise ratio (SNR) for the designed second order delta-sigma modulator is 75.6dB at an oversampling ratio of 64, 62.3dB at an oversampling ratio of 32 and 45.3dB at an oversampling ratio of 16. The implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ΔIDDQ testing of CMOS data converters is also presented. The BICS uses frequency as the output for fault detection in CUT. A fault is detected when the output frequency deviates more than ±10% from the reference frequency. The output frequencies of the BICS for various model parameters are simulated to check for the effect of process variation on the frequency deviation. A design for on-chip testability of CMOS ADC by linear ramp histogram technique using synchronous counter as register in code detection unit (CDU) is also presented. A brief overview of the histogram technique, the formulae used to calculate the ADC parameters, the design implemented in 0.5µm n-well CMOS process, the results and effectiveness of the design are described. Registers in this design are replaced by 6T-SRAM cells and a hardware optimized on-chip testability of CMOS ADC by linear ramp histogram technique using 6T-SRAM as register in CDU is presented. The on-chip linear ramp histogram technique can be seamlessly combined with ΔIDDQ technique for improved testability, increased fault coverage and reliable operation

A new BIST scheme for low-power and high-resolution DAC testing

A BIST scheme for testing on chip DAC is presented in this paper. We discuss the generation of on chip testing stimuli and the measurement of digital signals with a narrow-band digital filter. We validate the scheme with software simulation and point out the possibility of ADC BIST with verified DACicus-journals

Highly Linear 2,5-V CMOS ΣΔ Modulator for ADSL+

We present a 90-dB spurious-free dynamic range sigma–delta modulator (ΣΔM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25μm CMOS process with metal–insulator–metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within +/-0.85 and +/-0.80 LSB, respectively. The ΣΔ modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the ΣΔ modulator.This work was supported by the European Union under IST Project 29261/MIXMODEST and IST Project 2001-34283/TAMES-2 and the Spanish MCyT and the ERDF under Project TIC2001-0929/ADAVERE.This work was supported by the European Union under IST Project 29261/MIXMODEST and IST Project 2001-34283/TAMES-2 and the Spanish MCyT and the ERDF under Project TIC2001-0929/ADAVERE.Peer reviewe

Robust low power CMOS methodologies for ISFETs instrumentation

I have developed a robust design methodology in a 0.18 [Mu]m commercial CMOS process to circumvent the performance issues of the integrated Ions Sensitive Field Effect Transistor (ISFET) for pH detection. In circuit design, I have developed frequency domain signal processing, which transforms pH information into a frequency modulated signal. The frequency modulated signal is subsequently digitized and encoded into a bit-stream of data. The architecture of the instrumentation system consists of a) A novel front-end averaging amplifier to interface an array of ISFETs for converting pH into a voltage signal, b) A high linear voltage controlled oscillator for converting the voltage signal into a frequency modulated signal, and c) Digital gates for digitizing and differentiating the frequency modulated signal into an output bit-stream. The output bit stream is indistinguishable to a 1st order sigma delta modulation, whose noise floor is shaped by +20dB/decade. The fabricated instrumentation system has a dimension of 1565 [Mu] m 1565 [Mu] m. The chip responds linearly to the pH in a chemical solution and produces a digital output, with up to an 8-bit accuracy. Most importantly, the fabricated chips do not need any post-CMOS processing for neutralizing any trapped-charged effect, which can modulate on-chip ISFETs’ threshold voltages into atypical values. As compared to other ISFET-related works in the literature, the instrumentation system proposed in this thesis can cope with the mismatched ISFETs on chip for analogue-to-digital conversions. The design methodology is thus very accurate and robust for chemical sensing

A re-configurable pipeline ADC architecture with built-in self-test techniques

High-performance analog and mixed-signal integrated circuits are integral parts of today\u27s and future networking and communication systems. The main challenge facing the semiconductor industry is the ability to economically produce these analog ICs. This translates, in part, into the need to efficiently evaluate the performance of such ICs during manufacturing (production testing) and to come up with dynamic architectures that enable the performance of these ICs to be maximized during manufacturing and later when they\u27re operating in the field. On the performance evaluation side, this dissertation deals with the concept of Built-In-Self-Test (BIST) to allow the efficient and economical evaluation of certain classes of high-performance analog circuits. On the dynamic architecture side, this dissertation deals with pipeline ADCs and the use of BIST to dynamically, during production testing or in the field, re-configure them to produce better performing ICs.;In the BIST system proposed, the analog test signal is generated on-chip by sigma-delta modulation techniques. The performance of the ADC is measured on-chip by a digital narrow-band filter. When this system is used on the wafer level, significant testing time and thus testing cost can be saved.;A re-configurable pipeline ADC architecture to improve the dynamic performance is proposed. Based on dynamic performance measurements, the best performance configuration is chosen from a collection of possible pipeline configurations. This basic algorithm can be applied to many pipeline analog systems. The proposed grouping algorithm cuts down the number of evaluation permutation from thousands to 18 for a 9-bit ADC thus allowing the method to be used in real applications.;To validate the developments of this dissertation, a 40MS/s 9-bit re-configurable pipeline ADC was designed and implemented in TSMC\u27s 0.25mum single-poly CMOS digital process. This includes a fully differential folded-cascode gain-boosting operational amplifier with high gain and high unity-gain bandwidth. The experimental results strongly support the effectiveness of reconfiguration algorithm, which provides an average of 0.5bit ENOB improvement among the set of configurations. For many applications, this is a very significant performance improvement.;The BIST and re-configurability techniques proposed are not limited to pipeline ADCs only. The BIST methodology is applicable to many analog systems and the re-configurability is applicable to any analog pipeline system

Electronic bidirectional interfaces to the peripheral nervous system for prosthetic applications

The research presented in this thesis concerns the field of bioelectronics, in particular the work has been focused on the development of special electronic devices for neural signal acquisition and Peripheral Nervous System (PNS) stimulation. The final aim of the project in which this work is involved is in fact the realization of a prosthetic hand controlled using neural signals. The commercially available prosthesis are based on Electromyographic (EMG) signals, their use implies unnatural movements for the patient that needs a special training to develop the control capabilities over the mechanical limb. The proposed approach offers a number of advantages compared to the traditional prosthesis, first because the signals used are the same used to control the biologic limb, allowing a more comfortable solution for the patient that gets closer to feel the robotic hand as a natural extension of his/her body. Secondly, placing temperature and pressure sensors on the limb surface, it is possible to trasduce such information in an electrical current that, injected into the PNS, can restore the sensory feedback in amputees. The final goal of this research is the development of a fully implantable device able to perform a bidirectional communication between the robotic hand and the patient. Due to small area, low noise and low power constraints, the only possible way to reach this aim is the design of a full custom Integrated Circuit (IC). However a preliminary evaluation of the key design features, such as neural signal amplitudes and frequencies as well as stimulation shape parameters, is necessary in order to define clearly and precisely the design specifications. A low-cost and short implementation time device is then needed for this aim, the Components Off The Shelf (COTS) approach seems to be the best solution for this purpose. A Printed Circuit Board (PCB) with discrete components has been designed, developed and tested, the information extracted by the test results have been used to guide the IC design. The generation of electrical signals in biological cells, such as neural spikes, is possible thanks to ions that move across the cell membrane. In many applications it is important, not only to record the spikes, but also to measure these small currents in order to understand which electro-chemical processes are involved in the signal generation and to have a direct measurement of the ion channels involved in the reaction. Ion currents, in fact, play a key role in several physiological processes, in neural signal generation, but also in the maintenance of heartbeat and in muscle contraction. For this purpose, a system level implementation of a Read out circuit for ion channel current detection has been developed