228 research outputs found
Comparative analysis of VDMOS/LDMOS power transistors for RF amplifiers
A comparison between the RF performance of vertical and lateral power MOSFETs is presented. The role of each parasitic parameter in the assessment of the power gain, 1-dB compression point, efficiency, stability, and output matching is evaluated quantitatively using new analytical expressions derived from a ten-element model. This study reveals that the contribution of the parasitic parameter on degradation of performance depends upon the specific technology and generic perceptions of source inductance and feedback capacitance in VDMOS degradation may not always hold. This conclusion is supported by a detailed analysis of three devices of the same power rating from three different commercial vendors. A methodology for optimizing a device technology, specifically for RF performance and power amplifier performance is demonstrated
Fast physical models for Si LDMOS power transistor characterization
A new nonlinear, process-oriented, quasi-two-dimensional (Q2D) model is described for microwave laterally diffused MOS (LDMOS) power transistors. A set of one-dimensional energy transport equations are solved across a two-dimensional cross-section in a “current-driven” form. The model accounts for avalanche breakdown and gate conduction, and accurately predicts DC and microwave characteristics at execution speeds sufficiently fast for circuit simulation applications
Physics and technologies of silicon LDMOSFET for radio frequency applications
This thesis is devoted to the investigation of devices and technologies of Lateral Double-Diffused-
Metal-Oxide-Semiconductor-Field-Effect-Transistor for Radio Frequency (RP)
applications. Theoretical analysis and extensive 2-D process and device simulation results are
presented.
Theoretical analysis and simulations are carried out on RESURF LDMOS in both
bulk and SOI substrate in terms of breakdown characteristics, transconductance, on resistance
and CV characteristics.
Quasi-saturation is a common phenomenon in DMOS devices. In this work, the
dependence of quasi-saturation current on device physical and geometrical parameters is
investigated in SOI RP LDMOS. Physical insight is gained into quasi-saturation on SOI RP
LDMOS with different top silicon thickness and the same drift dose. It reveals that the
difference in thick and thin film SOI lies in the different potential drop in the drift region.
The influence of RESURF effect on quasi-saturation is also presented. It is shown that quasi-saturation
current level can be affected by RESURF due to its influence on the drift dose.
The mechanism of self-heating is presented and the influence of top silicon thickness,
buried oxide thickness, voltage bias is studied through simulations. The change of peak
temperature and its location with bias is due to the shift of electric field with voltage bias. A
back-etch structure and fabrication process have been proposed to achieve a superior thermal
performance. The negative differential conductance is not present in the non-isothermal IV
curves. The temperature rise in the back-etch structure is less than 114 of that in the bulk
structure.
An RP LDMOS with a step drift doping profile on SIMOX substrate is evaluated. The
fabrication process for the drift formation is proposed. The presented results demonstrate that
step drift device has higher breakdown voltage than the conventional uniformly doped (UD)
device, which provides the possibility to integrate LDMOS with low voltage CMOS for 28V
base station application. This structure also has the advantage of suppressed kink effect due
to the reduced electric field within the drift region. The step drift structure also features lower
capacitance, improved drain current saturation behaviour and reduced self-heating at class
AB bias point.
For the first time, a novel sandwich structure for lateral RF MOSFET has been analysed
based on silicon-on-nothing (SON) technology. The influence of device parameters on BV,
CV and thermal performance has been investigated. Partial SON structure is found preferable
in terms of heat conduct ability. Comparison on the electrical and thermal performance is
made between SON LDMOSFET and conventional SOI alternative with BV of 40V. It is
found that SON structure shows improvement in output capacitance and substrate loss.
However, the temperature rise in SON device is higher compared to SOI alternative. The
performance of the proposed sandwich SON structure has also been investigated in 28V base
station applications, which requires breakdown voltage of 80V
Design and Optimization of Superjunction Vertical DMOS Power Transistors using Sentaurus Device Simulation
Vertical double-diffused metal oxide semiconductor (VDMOS) power transistor has been studied. The use of superjunction (SJ) in the drift region of VDMOS has been evaluated using three-dimensional device simulation. All relevant physical models in Sentaurus are turned on. The VDMOS device doping profile is obtained from process simulation. The superjunction VDMOS performance in off-state breakdown voltage and specific on-resistance is compared with that in conventional VDMOS structure. In addition, electrical parameters such as threshold voltage and charge balance are also examined. Increasing the superjunction doping in the drift region of VDMOS reduces the on-resistance by 26%, while maintaining the same breakdown voltage and threshold voltage compared to that of the conventional VDMOS power transistor with similar device design without using a superjunction
Extended-p+ Stepped Gate (ESG) LDMOS for Improved Performance
In this paper, we propose a new Extended-p+ Stepped Gate (ESG) thin film SOI
LDMOS with an extended-p+ region beneath the source and a stepped gate
structure in the drift region of the LDMOS. The hole current generated due to
impact ionization is now collected from an n+p+ junction instead of an n+p
junction thus delaying the parasitic BJT action. The stepped gate structure
enhances RESURF in the drift region, and minimizes the gate-drain capacitance.
Based on two-dimensional simulation results, we show that the ESG LDMOS
exhibits approximately 63% improvement in breakdown voltage, 38% improvement in
on-resistance, 11% improvement in peak transconductance, 18% improvement in
switching speed and 63% reduction in gate-drain charge density compared with
the conventional LDMOS with a field plate.Comment: Journal Pape
High-Voltage Devices in Smart Power Technology
Tato práce se zabývá popisem základních vlastností LDMOS tranzistorů. V první části práce jsou rozebrány vlastnosti LDMOS tranzistorů, jejich základní parametry a techniky pro vylepšení parametrů těchto tranzistorů. V další části je rozebrána spolehlivost LDMOS tranzistorů, tato část popisuje bezpečnou pracovní oblast (SOA), injekci horkých nosičů (HCI) a negativní teplotní stabilitu (NBTI). Poslední teoretická část popisuje používané modely pro simulaci ESD událostí. Praktická část práce je zaměřena na simulaci základních parametrů PLDMOS a NLDMOS tranzistorů, porovnání simulovaných a změřených koncentračních profilů. Dále se práce zabývá simulacemi změny geometrických parametrů PLDMOS tranzistoru a vliv těchto změn na elektrické parametry. Poslední část práce tvoří TLP simulace, které zkoumají elektrické vlastnosti PLDMOS tranzistoru při použití jako ESD ochrana.This work describes fundamental characteristics of LDMOS transistors. In the first part of work are described properties of LDMOS transistors, the basic parameters and techniques to improve parameters of transistors. The next section discusses the reliability of LDMOS transistors. This section describes the safe operating area (SOA), hot carrier injection (HCI) and negative bias temperature instability (NBTI). The last theoretical section describes models used to simulate ESD events. The practical part is focused on simulation of the basic parameters PLDMOS and NLDMOS transistors and comparison of simulated and measured concentration profiles. Furthermore the thesis deals with simulation of the impact of changes in geometrical parameters of the PLDMOS transistor and the impact of these changes on the electrical parameters. The last part contains TLP simulations which examines electrical properties of PLDMOS transistor when is used as ESD protection.
Large signal design of silicon field effect transistors for linear radio frequency power amplifiers
EThOS - Electronic Theses Online ServiceGBUnited Kingdo
Comparative study of RESURF Si/SiC LDMOSFETs for high-temperature applications using TCAD modeling
This paper analyses the effect of employing an Si on semi-insulating SiC (Si/SiC) device architecture for the implementation of 600-V LDMOSFETs using junction isolation and dielectric isolation reduced surface electric field technologies for high-temperature operations up to 300 °C. Simulations are carried out for two Si/SiC transistors designed with either PN or silicon-on-insulator (SOI) and their equivalent structures employing bulk-Si or SOI substrates. Through comparisons, it is shown that the Si/SiC devices have the potential to operate with an offstate leakage current as low as the SOI device. However, the low-side resistance of the SOI LDMOSFET is smaller in value and less sensitive to temperature, outperforming both Si/SiC devices. Conversely, under high-side configurations, the Si/SiC transistors have resistances lower than that of the SOI at high substrate bias, and invariable with substrate potential up to −200 V, which behaves similar to the bulkSi LDMOS at 300 K. Furthermore, the thermal advantage of the Si/SiC over other structures is demonstrated by using a rectangle power pulse setup in Technology Computer-Aided design simulations
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