The Essential Role and the Continuous Evolution of Modulation Techniques for Voltage-Source Inverters in the Past, Present, and Future Power Electronics

The cost reduction of power-electronic devices, the increase in their reliability, efficiency, and power capability, and lower development times, together with more demanding application requirements, has driven the development of several new inverter topologies recently introduced in the industry, particularly medium-voltage converters. New more complex inverter topologies and new application fields come along with additional control challenges, such as voltage imbalances, power-quality issues, higher efficiency needs, and fault-tolerant operation, which necessarily requires the parallel development of modulation schemes. Therefore, recently, there have been significant advances in the field of modulation of dc/ac converters, which conceptually has been dominated during the last several decades almost exclusively by classic pulse-width modulation (PWM) methods. This paper aims to concentrate and discuss the latest developments on this exciting technology, to provide insight on where the state-of-the-art stands today, and analyze the trends and challenges driving its future

Reduction of total harmonic distortion in power inverters

The output voltage of PWM power inverters shows harmonic distortion due to several causes; the main ones are the modulation algorithm, nonlinearities in the output filter, dead times, voltage drops across the switches and modulation of the dc bus voltage. The distortion is more evident when using low dc bus voltages. As a result, motors driven by these inverters have important torque pulsations. This work proposes to reduce the distortion produced by dead times and voltage drops across the switches using a simple algorithm that recalculates the width of each PWM pulse, while preserving the ideal area. By simulation, the THD was reduced from 18% to 0.29% in a single-phase inverter. The proposed algorithm only needs products and sums, so it is suitable for being implemented on a DSP with a very low processing load.Fil: Oliva, Alejandro Raul. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Chiacchiarini, Hector Gerardo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Aymonino, Oscar Andres. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Mandolesi, Pablo Sergio. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; Argentin

New Dead-Time Compensation Method of Power Inverter using Carrier Based Sinusoidal Pulse-Width Modulation

A new dead-time compensation method of power inverter circuits is suggested and presented in this paper. The proposed method utilizes carrier based sinusoidal pulse width modulation technique to produce driving signals of the inverter power switches with dead-time correction capability. The proposed method able to eliminate dead-time effects such as reducing the waveform distortion of the inverter output current, and increasing the fundamental component amplitude of output current. An analysis of the proposed method is presented. Some computer simulations were carried out to investigate the principle operation, and to test performance of the new method. The developed method was validated through experimental test of H-bridge voltage source inverter circuits. The data obtained from the computer simulation and prototype experiments have confirmed that that the proposed method worked well compensating the dead-time in the voltage source power inverter circuits

Suppression of line voltage related distortion in current controlled grid connected inverters

The influence of selected control strategies on the level of low-order current harmonic distortion generated by an inverter connected to a distorted grid is investigated through a combination of theoretical and experimental studies. A detailed theoretical analysis, based on the concept of harmonic impedance, establishes the suitability of inductor current feedback versus output current feedback with respect to inverter power quality. Experimental results, obtained from a purpose-built 500-W, three-level, half-bridge inverter with an L-C-L output filter, verify the efficacy of inductor current as the feedback variable, yielding an output current total harmonic distortion (THD) some 29% lower than that achieved using output current feedback. A feed-forward grid voltage disturbance rejection scheme is proposed as a means to further reduce the level of low-order current harmonic distortion. Results obtained from an inverter with inductor current feedback and optimized feed-forward disturbance rejection show a THD of just 3% at full-load, representing an improvement of some 53% on the same inverter with output current feedback and no feed-forward compensation. Significant improvements in THD were also achieved across the entire load range. It is concluded that the use of inductor current feedback and feed-forward voltage disturbance rejection represent cost–effect mechanisms for achieving improved output current quality

A holistic DC link architecture design method for multiphase Integrated Modular Motor Drives

This article describes a holistic DC link architecture design method that considers the end-application of the drive and its corresponding constraints e.g. the maximum battery ripple current for a battery-supplied inverter. Also, the levers that are available to comply with the design criteria are presented e.g. the use of interleaved carrier waves. This holistic approach will result in a feasible and performant Integrated Modular Motor Drive from an application point of view. Finally, a platform is presented that was developed for feasibility and performance assessment of various DC link architectures obtained from the holistic design approach. The platform comprises a fifteen phase integrable modular motor drive for an Axial Flux Permanent Magnet Synchronous Machine. It allows non-intrusive reconfiguration of the DC link architecture and implementation of various control strategies and interleaved PWM schemes

A multi-level converter with a floating bridge for open-ended winding motor drive applications

This paper presents a dual three phase open end winding induction motor drive. The drive consists of a three phase induction machine with open stator phase windings and dual bridge inverter supplied from a single DC voltage source. To achieve multi-level output voltage waveforms a floating capacitor bank is used for the second of the dual bridges. The capacitor voltage is regulated using redundant switching states at half of the main dc link voltage. This particular voltage ratio (2:1) is used to create a multi-level output voltage waveform with three levels. A modified modulation scheme is used to improve the waveform quality of this dual inverter. This paper also compares the losses in dual inverter system in contrast with single sided three-level NPC converter. Finally, detailed simulation and experimental results are presented for the motor drive operating as an open loop v/f controlled motor drive and as a closed loop field oriented motor controller

Harmonic reduction using Particle Swarm Optimization based SHE Modulation Technique in Asymmetrical DC-AC Converter

Many inverters play an important role in transmitting and processing energy to power system networks. To reduce the cost and size of multilevel inverters, various topologies have been included in the literature. But these topologies do not look at the complete harmonic distortion in the output waveform. In this study, a modern multilevel inverter structure, a mutated H-bridge inverter is adopted that demands a small amount of switches, driver circuits, power diodes and DC voltage sources compared to conventional multilevel inverters to produce the required level in the output voltage. The mutated H-bridge converter uses a nearest-level control method, produces high value of total harmonic at the output voltage and low-level harmonics content is also high, which is more dangerous than high-order harmonics. Therefore, the selective harmonic elimination (SHE) method is used to reduce the low frequency harmonics and the total harmonic distortion to the output voltage. Comparison of complete harmonic deviation and low-level harmonic content using the above-mentioned control strategies on the 31-level inverter is presented. Simulation studies confirm the performance of a 31-level inverter with low-order harmonics and a complete harmonic distortion using the SHE process. The effectiveness and accuracy of the SHE in producing 31 level waveform is demonstrated by utilizing the test outcomes and the THD found is of the order of 2.8%, 1.7%, 1.7% and 1% for the modulation index values of 0.5590, 0.7440, and 0.8380 and 0.9110 respectively

A Space Vector PWM With Common-Mode Voltage Elimination for Open-End Winding Five-Phase Drives With a Single DC Supply

Open-end winding three-phase drive topologies have been extensively investigated in the last two decades. In the majority of cases supply of the inverters at the two sides of the winding is provided from isolated dc sources. Recently, studies related to multiphase open-end winding drives have also been conducted, using isolated dc sources at the two winding sides. This paper investigates for the first time a five-phase open-end winding configuration, which is obtained by connecting a two-level five-phase inverter at each side of the stator winding, with both inverters supplied from a common dc source. In such a configuration it is essential to eliminate the common-mode voltage (CMV) that is inevitably created by usual PWM techniques. Based on the vector space decomposition (VSD), the switching states that create zero CMV are indentified and plotted. A space vector pattern with large redundancy of switching states is obtained. Suitable space vectors are then selected to realize the required voltage reference at the machine terminals with zero CMV. The large number of redundant states enables some freedom in the choice of switching states to impress these space vectors. Out of numerous possibilities, two particular switching sequences are chosen for further investigation. Both are implemented in an experimental setup, and the results are presented and discussed. © 2013 IEEE

Online Switching Time Monitoring of SiC Devices Using Intelligent Gate Driver for Converter Performance Improvement

Most intelligent gate drivers designed for new state of the art WBG devices typically only focus on protection and driving capabilities of the devices. This paper introduces an intelligent gate driver that incorporates online switching time monitoring of silicon carbide (SiC) devices. For this specific case study, three timing conditions (turn-off delay time, turn-off time, and voltage commutation time) of a SiC phase-leg are online monitored. This online monitoring system is achieved through transient detection circuits and a micro-controller. These timing conditions are then utilized to develop converter-level benefits for a voltage-source inverter application using SiC devices. Junction temperature monitoring is realized through turn-off delay time monitoring. Dead-time optimization is achieved with turn-off time monitoring. Dead-time compensation is obtained with turn-off time and voltage commutation time monitoring. The case study converter assembled for testing purposes is a half-bridge inverter using two SiC devices in a phase-leg configuration. All timing conditions are correctly monitored within reasonable difference of the actual condition time. The half-bridge inverter can operate at 600 V DC input and successfully obtain a junction temperature measurement through monitored turn-off delay time and the calibration curve. In addition, dead-time control is realized to reduce device power loss and improve AC output power quality. Furthermore, the proposed online time monitoring system is board-level integrated with the gate driver and suitable for the chip level integration, enabling this practical approach to be cost-effective for end users