Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve

System-on-Package Low-Power Telemetry and Signal Conditioning unit for Biomedical Applications

Recent advancements in healthcare monitoring equipments and wireless communication technologies have led to the integration of specialized medical technology with the pervasive wireless networks. Intensive research has been focused on the development of medical wireless networks (MWN) for telemedicine and smart home care services. Wireless technology also shows potential promises in surgical applications. Unlike conventional surgery, an expert surgeon can perform the surgery from a remote location using robot manipulators and monitor the status of the real surgery through wireless communication link. To provide this service each surgical tool must be facilitated with smart electronics to accrue data and transmit the data successfully to the monitoring unit through wireless network. To avoid unwieldy wires between the smart surgical tool and monitoring units and to reap the benefit of excellent features of wireless technology, each smart surgical tool must incorporate a low-power wireless transmitter. Low-power transmitter with high efficiency is essential for short range wireless communication. Unlike conventional transmitters used for cellular communication, injection-locked transmitter shows greater promises in short range wireless communication. The core block of an injection-locked transmitter is an injection-locked oscillator. Therefore, this research work is directed towards the development of a low-voltage low-power injection-locked oscillator which will facilitate the development of a low-power injection-locked transmitter for MWN applications. Structure of oscillator and types of injection are two crucial design criteria for low-power injection-locked oscillator design. Compared to other injection structures, body-level injection offers low-voltage and low-power operation. Again, conventional NMOS/PMOS-only cross-coupled LC oscillator can work with low supply voltage but the power consumption is relatively high. To overcome this problem, a self-cascode LC oscillator structure has been used which provides both low-voltage and low-power operation. Body terminal coupling is used with this structure to achieve injection-locking. Simulation results show that the self-cascode structure consumes much less power compared to that of the conventional structure for the same output swing while exhibiting better phase noise performance. Usage of PMOS devices and body bias control not only reduces the flicker noise and power consumption but also eliminates the requirements of expensive fabrication process for body terminal access

Design of Power Optimized circuit of LC Voltage Controlled Oscillator for use in GSM Handsets

The recent performance requirements for mobile phones have been extending its area of interest. Handsets need to have high resolution graphics, pictures, and applications. Consequently, the requirement for a longer battery life has become a bare necessity. This makes optimization of power a critical issue. Along with this cell phones need to be thin and have light weight. A major portion of the power consumption of the handsets can be attributed to the LC oscillators used in the system. A Voltage Controlled Oscillator plays an important role in any communication system. It provides the frequency signal for down-conversion of input signals and also the carrier signals for the modulating signal. Proper amplitude and low phase noise are two important criteria to achieve suitable performance for a VCO in any transceiver system. The strong combination of low phase noise specifications with very low power consumption (battery operation) forces designers to use LC-VCOs. A great research effort has been done in the design of integrated voltage controlled oscillators (VCOs) using integrated or external resonators, but as their power consumption still cannot be unacceptable, today’s mobile phones commonly use external LC-VCO modules. Inductors used in these oscillators are usually bulky and have high power consumption. The low power LC oscillator increases the standby time, thus improving the battery life. Extended battery life provides processing power at lower clock speeds, enabling low leakage process that optimizes power consumption and increases battery time. Also provides integrated and sophisticated systems with improved power management. The main purpose of this project is to design a circuit for LC VCO to be used in GSM system with a tuning rage of 3-4GHz. Since the phase noise requirement for the system is less than 150dBc/Hz at 20 KHz offset. Also for a GSM system, the size of the inductor used in the oscillator is a major issue in determining its overall size, efforts will be made to optimize the size of the inductor as well

Power-efficient current-mode analog circuits for highly integrated ultra low power wireless transceivers

In this thesis, current-mode low-voltage and low-power techniques have been applied to implement novel analog circuits for zero-IF receiver backend design, focusing on amplification, filtering and detection stages. The structure of the thesis follows a bottom-up scheme: basic techniques at device level for low voltage low power operation are proposed in the first place, followed by novel circuit topologies at cell level, and finally the achievement of new designs at system level. At device level the main contribution of this work is the employment of Floating-Gate (FG) and Quasi-Floating-Gate (QFG) transistors in order to reduce the power consumption. New current-mode basic topologies are proposed at cell level: current mirrors and current conveyors. Different topologies for low-power or high performance operation are shown, being these circuits the base for the system level designs. At system level, novel current-mode amplification, filtering and detection stages using the former mentioned basic cells are proposed. The presented current-mode filter makes use of companding techniques to achieve high dynamic range and very low power consumption with for a very wide tuning range. The amplification stage avoids gain bandwidth product achieving a constant bandwidth for different gain configurations using a non-linear active feedback network, which also makes possible to tune the bandwidth. Finally, the proposed current zero-crossing detector represents a very power efficient mixed signal detector for phase modulations. All these designs contribute to the design of very low power compact Zero-IF wireless receivers. The proposed circuits have been fabricated using a 0.5μm double-poly n-well CMOS technology, and the corresponding measurement results are provided and analyzed to validate their operation. On top of that, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.Programa Oficial de Doctorado en Tecnologías de las Comunicaciones (RD 1393/2007)Komunikazioen Teknologietako Doktoretza Programa Ofiziala (ED 1393/2007

Equalized on-chip interconnect : modeling, analysis, and design

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.Includes bibliographical references (p. 115-118).This thesis work explores the use of equalization techniques to improve throughput and reduce power consumption of on-chip interconnect. A theoretical model for an equalized on-chip interconnect is first suggested to provide mathematical formulation for the link behavior. Based on the model, a fast-design space exploration methodology is demonstrated to search for the optimal link design parameters (wire and circuit) and to generate the optimal performance-power trade-off curve for the equalized interconnects. This thesis also proposes new circuit techniques, which improve the revealed demerits of the conventional circuit topologies. The proposed charge-injection transmitter directly conducts pre-emphasis current from the supply into the channel, eliminating the power overhead of analog current subtraction in the conventional transmit pre-emphasis, while significantly relaxing the driver coefficient accuracy requirements. The transmitter utilizes a power efficient nonlinear driver by compensating non-linearity with pre-distorted equalization coefficients. A trans-impedance amplifier at the receiver achieves low static power consumption, large signal amplitude, and high bandwidth by mitigating limitations of purely-resistive termination. A test chip is fabricated in 90-nm bulk CMOS technology and tested over a 10 mm, 2[micro]m pitched on-chip differential wire. The transceiver consumes 0.37-0.63 pJ/b with 2-6 Gb/s/ch.by Byungsub Kim.Ph.D

Design of Tunable Low-Noise Amplifier in 0.13um CMOS Technology for Multistandard RF Transceivers

The global market of mobile and wireless communications is witnessing explosive growth in size as well as radical changes. Third generation (3G) wireless systems have recently been deployed and some are still in the process. 3G wireless systems promise integration of voice and data communications with higher data rates and a superior quality of service compared to second generation systems. Unfortunately, more and more communication standards continue to be developed which ultimately requires specific RF/MW and baseband communication integrated circuits that are designed for functionality and compatibility with a specific type of network. Although communication devices such as cellular phones integrate different services such as voice, Bluetooth, GPS, and WLAN, each service requires its own dedicated radio transceiver which results in high power consumption and larger PCB area usage. With the rapid advances in silicon CMOS integrated circuit technology combined with extensive research, a global solutionswhich aims at introducing a global communication system that encompasses all communication standards appears to be emerging. State of the art CMOS technology not only has the capability of operation in the GHz range, but it also provides the advantage of low cost and high level of integration. These features propel CMOS technology as the ideal candidate for current trends, which currently aim to integrate more RF/MW circuits on the same chip. Armed with such technology ideas such as software radio look more attainable than they ever were in the past. Unfortunately, realizing true software radio for mobile applications still remains a tremendous challenge since it requires a high sampling rate and a wide-bandwidth Analog-to-Digital converter which is extremely power hungry and not suitable for battery operated mobile devices. Another approach to realize a flexible and reconfigurable RF/MW transceiver that could operate in a diverse mobile environment and provides a multiband and multistandard solution. The work presented in this thesis focuses on the design of an integrated and tunable low-noise amplifier as part of software defined radio (SDR)

Power System Stability Analysis Using Wide Area Measurement System

Advances in wide area measurement systems have transformed power system operation from simple visualization, state estimation, and post-mortem analysis tools to real-time protection and control at the systems level. Transient disturbances (such as lightning strikes) exist only for a fraction of a second but create transient stability issues and often trigger cascading type failures. The most common practice to prevent instabilities is with local generator out-of-step protection. Unfortunately, out-of-step protection operation of generators may not be fast enough, and an instability may take down nearby generators and the rest of the system by the time the local generator relay operates. Hence, it is important to assess power system stability over transmission lines as soon as the transient instability is detected instead of relying on purely localized out-of-step protection in generators. This thesis proposes a synchrophasor-based out-of-step prediction methodology at the transmission line level using wide area measurements from optimal phasor measurement unit (PMU) locations in the interconnected system. Voltage and current measurements from wide area measurement systems (WAMS) are utilized to find the swing angles. The proposed scheme was used to predict the first swing out-of-step condition in a Western Systems Coordinating Council (WSCC) 9 bus power system. A coherency analysis was first performed in this multi-machine system to determine the two coherent groups of generators. The coherent generator groups were then represented with a two-machine equivalent system, and the synchrophasor-based out-of-step prediction algorithm then applied to the reduced equivalent system. The coherency among the group of generators was determined within 100 ms for the contingency scenarios tested. The proposed technique is able to predict the instability 141.66 to 408.33 ms before the system actually reaches out-of-step conditions. The power swing trajectory is either a steady-state trajectory, monotonically increasing type (when the system becomes unstable), or oscillatory type (under stable conditions). Un- der large disturbance conditions, the swing could also become non-stationary. The mean and variance of the signal is not constant when it is monotonically increasing or non-stationary. An autoregressive integrated (ARI) approach was developed in this thesis, with differentiation of two successive samples done to make the mean and variance constant and facilitate time series prediction of the swing curve. Electromagnetic transient simulations with a real-time digital simulator (RTDS) were used to test the accuracy of the proposed algorithm with respect to predicting transient in- stability conditions. The studies show that the proposed method is computationally efficient and accurate for larger power systems. The proposed technique was also compared with a conventional two blinder technique and swing center voltage method. The proposed method was also implemented with actual PMU measurements from a relay (General Electric (GE) N60 relay). The testing was carried out with an interface between the N60 relay and the RTDS. The WSCC 9 bus system was modeled in the simulator and the analog time signals from the optimal location in the network communicated to the N60 relay. The synchrophasor data from the PMUs in the N60 were used to back-calculate the rotor angles of the generators in the system. Once the coherency was established, the swing curves for the coherent group of generators were found from time series prediction (ARI model). The test results with the actual PMUs match quite well with the results obtained from virtual PMU-based testing in the RTDS. The calculation times for the time series prediction are also very small. This thesis also discusses a novel out-of-step detection technique that was investigated in the course of this work for an IEEE Power Systems Relaying Committee J-5 Working Group document using real-time measurements of generator accelerating power. Using the derivative or second derivative of a measurement variable significantly amplifies the noise term and has limited the actual application of some methods in the literature, such as local measurements of voltage or voltage deviations at generator terminals. Another problem with the voltage based methods is taking an average over a period; the intermediate values cancel out and, as a result, just the first and last sample values are used to find the speed. This effectively means that the sample values in between are not used. The first solution proposed to overcome this is a polynomial fitting of the points of the calculated derivative points (to calculate speed). The second solution is the integral of the accelerating power method (this eliminates taking a derivative altogether). This technique shows the direct relationship of electrical power deviation to rotor acceleration and the integral of accelerating power to generator speed deviation. The accelerating power changes are straightforward to measure and the values obtained are more stable during transient conditions. A single machine infinite bus (SMIB) system was used for the purpose of verifying the proposed local measurement based method