Low-power CMOS digital-pixel Imagers for high-speed uncooled PbSe IR applications

This PhD dissertation describes the research and development of a new low-cost medium wavelength infrared MWIR monolithic imager technology for high-speed uncooled industrial applications. It takes the baton on the latest technological advances in the field of vapour phase deposition (VPD) PbSe-based medium wavelength IR (MWIR) detection accomplished by the industrial partner NIT S.L., adding fundamental knowledge on the investigation of novel VLSI analog and mixed-signal design techniques at circuit and system levels for the development of the readout integrated device attached to the detector. The work supports on the hypothesis that, by the use of the preceding design techniques, current standard inexpensive CMOS technologies fulfill all operational requirements of the VPD PbSe detector in terms of connectivity, reliability, functionality and scalability to integrate the device. The resulting monolithic PbSe-CMOS camera must consume very low power, operate at kHz frequencies, exhibit good uniformity and fit the CMOS read-out active pixels in the compact pitch of the focal plane, all while addressing the particular characteristics of the MWIR detector: high dark-to-signal ratios, large input parasitic capacitance values and remarkable mismatching in PbSe integration. In order to achieve these demands, this thesis proposes null inter-pixel crosstalk vision sensor architectures based on a digital-only focal plane array (FPA) of configurable pixel sensors. Each digital pixel sensor (DPS) cell is equipped with fast communication modules, self-biasing, offset cancellation, analog-to-digital converter (ADC) and fixed pattern noise (FPN) correction. In-pixel power consumption is minimized by the use of comprehensive MOSFET subthreshold operation. The main aim is to potentiate the integration of PbSe-based infra-red (IR)-image sensing technologies so as to widen its use, not only in distinct scenarios, but also at different stages of PbSe-CMOS integration maturity. For this purpose, we posit to investigate a comprehensive set of functional blocks distributed in two parallel approaches: • Frame-based “Smart” MWIR imaging based on new DPS circuit topologies with gain and offset FPN correction capabilities. This research line exploits the detector pitch to offer fully-digital programmability at pixel level and complete functionality with input parasitic capacitance compensation and internal frame memory. • Frame-free “Compact”-pitch MWIR vision based on a novel DPS lossless analog integrator and configurable temporal difference, combined with asynchronous communication protocols inside the focal plane. This strategy is conceived to allow extensive pitch compaction and readout speed increase by the suppression of in-pixel digital filtering, and the use of dynamic bandwidth allocation in each pixel of the FPA. In order make the electrical validation of first prototypes independent of the expensive PbSe deposition processes at wafer level, investigation is extended as well to the development of affordable sensor emulation strategies and integrated test platforms specifically oriented to image read-out integrated circuits. DPS cells, imagers and test chips have been fabricated and characterized in standard 0.15μm 1P6M, 0.35μm 2P4M and 2.5μm 2P1M CMOS technologies, all as part of research projects with industrial partnership. The research has led to the first high-speed uncooled frame-based IR quantum imager monolithically fabricated in a standard VLSI CMOS technology, and has given rise to the Tachyon series [1], a new line of commercial IR cameras used in real-time industrial, environmental and transportation control systems. The frame-free architectures investigated in this work represent a firm step forward to push further pixel pitch and system bandwidth up to the limits imposed by the evolving PbSe detector in future generations of the device.La present tesi doctoral descriu la recerca i el desenvolupament d'una nova tecnologia monolítica d'imatgeria infraroja de longitud d'ona mitja (MWIR), no refrigerada i de baix cost, per a usos industrials d'alta velocitat. El treball pren el relleu dels últims avenços assolits pel soci industrial NIT S.L. en el camp dels detectors MWIR de PbSe depositats en fase vapor (VPD), afegint-hi coneixement fonamental en la investigació de noves tècniques de disseny de circuits VLSI analògics i mixtes pel desenvolupament del dispositiu integrat de lectura unit al detector pixelat. Es parteix de la hipòtesi que, mitjançant l'ús de les esmentades tècniques de disseny, les tecnologies CMOS estàndard satisfan tots els requeriments operacionals del detector VPD PbSe respecte a connectivitat, fiabilitat, funcionalitat i escalabilitat per integrar de forma econòmica el dispositiu. La càmera PbSe-CMOS resultant ha de consumir molt baixa potència, operar a freqüències de kHz, exhibir bona uniformitat, i encabir els píxels actius CMOS de lectura en el pitch compacte del pla focal de la imatge, tot atenent a les particulars característiques del detector: altes relacions de corrent d'obscuritat a senyal, elevats valors de capacitat paràsita a l'entrada i dispersions importants en el procés de fabricació. Amb la finalitat de complir amb els requisits previs, es proposen arquitectures de sensors de visió de molt baix acoblament interpíxel basades en l'ús d'una matriu de pla focal (FPA) de píxels actius exclusivament digitals. Cada píxel sensor digital (DPS) està equipat amb mòduls de comunicació d'alta velocitat, autopolarització, cancel·lació de l'offset, conversió analògica-digital (ADC) i correcció del soroll de patró fixe (FPN). El consum en cada cel·la es minimitza fent un ús exhaustiu del MOSFET operant en subllindar. L'objectiu últim és potenciar la integració de les tecnologies de sensat d'imatge infraroja (IR) basades en PbSe per expandir-ne el seu ús, no només a diferents escenaris, sinó també en diferents estadis de maduresa de la integració PbSe-CMOS. En aquest sentit, es proposa investigar un conjunt complet de blocs funcionals distribuïts en dos enfocs paral·lels: - Dispositius d'imatgeria MWIR "Smart" basats en frames utilitzant noves topologies de circuit DPS amb correcció de l'FPN en guany i offset. Aquesta línia de recerca exprimeix el pitch del detector per oferir una programabilitat completament digital a nivell de píxel i plena funcionalitat amb compensació de la capacitat paràsita d'entrada i memòria interna de fotograma. - Dispositius de visió MWIR "Compact"-pitch "frame-free" en base a un novedós esquema d'integració analògica en el DPS i diferenciació temporal configurable, combinats amb protocols de comunicació asíncrons dins del pla focal. Aquesta estratègia es concep per permetre una alta compactació del pitch i un increment de la velocitat de lectura, mitjançant la supressió del filtrat digital intern i l'assignació dinàmica de l'ample de banda a cada píxel de l'FPA. Per tal d'independitzar la validació elèctrica dels primers prototips respecte a costosos processos de deposició del PbSe sensor a nivell d'oblia, la recerca s'amplia també al desenvolupament de noves estratègies d'emulació del detector d'IR i plataformes de test integrades especialment orientades a circuits integrats de lectura d'imatge. Cel·les DPS, dispositius d'imatge i xips de test s'han fabricat i caracteritzat, respectivament, en tecnologies CMOS estàndard 0.15 micres 1P6M, 0.35 micres 2P4M i 2.5 micres 2P1M, tots dins el marc de projectes de recerca amb socis industrials. Aquest treball ha conduït a la fabricació del primer dispositiu quàntic d'imatgeria IR d'alta velocitat, no refrigerat, basat en frames, i monolíticament fabricat en tecnologia VLSI CMOS estàndard, i ha donat lloc a Tachyon, una nova línia de càmeres IR comercials emprades en sistemes de control industrial, mediambiental i de transport en temps real.Postprint (published version

Power-efficient Circuit Architectures for Receivers Leveraging Nanoscale CMOS

Cellular and mobile communication markets, together with CMOS technology scaling, have made complex systems-on-chip integrated circuits (ICs) ubiquitous. Moving towards the internet of things that aims to extend this further requires ultra-low power and efficient radio communication that continues to take advantage of nanoscale CMOS processes. At the heart of this lie orthogonal challenges in both system and circuit architectures of current day technology. By enabling transceivers at center frequencies ranging in several tens of GHz, modern CMOS processes support bandwidths of up to several GHz. However, conventional narrowband architectures cannot directly translate or trade-off these speeds to lower power consumption. Pulse-radio UWB (PR-UWB), a fundamentally different system of communication enables this trade-off by bit-level duty-cycling i.e., power-gating and has emerged as an alternative to conventional narrowband systems to achieve better energy efficiency. However, system-level challenges in the implementation of transceiver synchronization and duty-cycling have remained an open challenge to realize the ultra-low power numbers that PR-UWB promises. Orthogonally, as CMOS scaling continues, approaching 28nm and 14nm in production digital processes, the key transistor characteristics have rapidly changed. Changes in supply voltage, intrinsic gain and switching speeds have rendered conventional analog circuit design techniques obsolete, since they do not scale well with the digital backend engines that dictate scaling. Consequently, circuit architectures that employ time-domain processing and leverage the faster switching speeds have become attractive. However, they are fundamentally limited by their inability to support linear domain-to-domain conversion and hence, have remained un-suited to high-performance applications. Addressing these requirements in different dimensions, two pulse-radio UWB receiver and a continuous-time filter silicon prototypes are presented in this work. The receiver prototypes focus on system level innovation while the filter serves as a demonstration vehicle for novel circuit architectures developed in this work. The PR-UWB receiver prototypes are implemented in a 65nm LP CMOS technology and are fully integrated solutions. The first receiver prototype is a compact UWB receiver front end operating at 4.85GHz that is aggressively duty-cycled. It occupies an active area of only 0.4 mm², thanks to the use of few inductors and RF G_m-C filters and incorporates an automatic-threshold-recovery-based demodulator for digitization. The prototype achieves a sensitivity of -88dBm at a data rate of 1Mbps (for a BER of 10^-3), while achieving the lowest energy consumption gradient (dP/df_data=450pJ/bit) amongst other receivers operating in the lower UWB band, for the same sensitivity. However, this prototype is limited by idle-time power consumption (e.g., bias) and lacks synchronization capability. A fully self-duty-cycled and synchronized UWB pulse-radio receiver SoC targeted at low-data-rate communication is presented as the second prototype. The proposed architecture builds on the automatic-threshold-recovery-based demodulator to achieve synchronization using an all-digital clock and data recovery loop. The SoC synchronizes with the incoming pulse stream from the transmitter and duty-cycles itself. The SoC prototype achieves a -79.5dBm, 1Mbps-normalized sensitivity for a >5X improvement over the state of the art in power consumption (375pJ/bit), thanks to aggressive signal path and bias circuit duty-cycling. The SoC is fully integrated to achieve RF-in to bit-out operation and can interface with off-chip, low speed digital components. Finally, switched-mode signal processing, a signal processing paradigm that enables the design of highly linear, power-efficient feedback amplifiers is presented. A 0.6V continuous-time filter prototype that demonstrates the advantages of this technique is presented in a 65nm GP CMOS process. The filter draws 26.2mW from the supply while operating at a full-scale that is 73% of the V_dd, a bandwidth of 70MHz and a peak signal-to-noise-and-distortion ratio (SNDR) of 55.8dB. This represents a 2-fold improvement in full-scale and a 10-fold improvement in the bandwidth over state-of-the-art filter implementations, while demonstrating excellent linearity and signal-to-noise ratio. To sum up, innovations spanning both system and circuit architectures that leverage the speeds of nanoscale CMOS processes to enable power-efficient solutions to next-generation wireless receivers are presented in this work

Design of a 2.4 Ghz BAW-Based CMOS Transmitter

In recent years, bulk acoustic wave resonators (BAW) in combination with RF circuits have shown a big potential in achieving the low-power consumption and miniaturization level required to address wireless sensor nodes (WSN) applications. A lot of work has been focused on the receiver side, by integrating BAW resonators with low noise amplifiers (LNA) and in frequency synthesis with the design of BAW-based local oscillators, most of them working at fixed frequency due to their limited tuning range. At the architectural level, this has forced the implementation of several single channel transceivers. This thesis aims at exploring the use of BAW resonators in the transmitter, proposing an architecture capable of taking full advantage of them. The main objective is to develop a transmitter for WSN multi-channel applications able to cover the whole 2.4 GHz ISM band and enable the compatibility with wide-spread standards like Bluetooth and Bluetooth Low Energy. Typical transmissions should thus range from low data rates (typically tens of kb/s) to medium data rates (1 Mb/s), with FSK and GFSK modulation schemes, should be centered on any of the channels provided by these standards and cover a maximum transmission range of some tens of meters. To achieve these targets and circumvent the limited tuning range of the BAW oscillator, an up-conversion transmitter using wide IF is used. The typical spurs problems related to this transmitter architecture are addressed by using a combined suppression based on SSB mixing and selective amplification. The latter is achieved by cointegration of a high efficiency power amplifier with BAW resonators, which allows performing spurs filtering while preserving the efficiency. In particular the selective amplifier is designed by including in the PA analysis the BAW resonator parameters, which allows integrating the BAW filter into the passive network loading the amplifier, participating in the drain voltage shaping. Finally, the frequency synthesis section uses a fractional division plus LC PLL filtering and further integer division to generate the IF signals and exploit the very-low BAW oscillator phase noise. The transmitter has been integrated in a 0.18 µm standard digital CMOS technology. It allows addressing the whole 80 MHz wide 2.4 GHz ISM band. The unmodulated RF frequency carrier demonstrates a very-low phase noise of –136 dBc/Hz at 1 MHz offset. The IF spurs are maintained lower than –48 dBc, satisfying the international regulations for output power up to 10 dBm without the use of any quadrature error compensation in the transmitter. This is achieved thanks to the rejection provided by the SSB mixer and the selective amplifier, which can reach drain efficiency of up to 24% with integrated inductances, including the insertion losses of the BAW filter. The transmitter consumes 35.3 mA at the maximum power of 5.4 dBm under 1.6 V (1.2 V for the PA), while transmitting a 1 Mb/s GFSK signal and complying with both Bluetooth and Bluetooth Low Energy relative and absolute spectrum requirements

Analysis and Design of Silicon based Integrated Circuits for Radio Frequency Identification and Ranging Systems at 24GHz and 60GHz Frequency Bands

This scientific research work presents the analysis and design of radio frequency (RF) integrated circuits (ICs) designed for two cooperative RF identification (RFID) proof of concept systems. The first system concept is based on localizable and sensor-enabled superregenerative transponders (SRTs) interrogated using a 24GHz linear frequency modulated continuous wave (LFMCW) secondary radar. The second system concept focuses on low power components for a 60GHz continuous wave (CW) integrated single antenna frontend for interrogating close range passive backscatter transponders (PBTs). In the 24GHz localizable SRT based system, a LFMCW interrogating radar sends a RF chirp signal to interrogate SRTs based on custom superregenerative amplifier (SRA) ICs. The SRTs receive the chirp and transmit it back with phase coherent amplification. The distance to the SRTs are then estimated using the round trip time of flight method. Joint data transfer from the SRT to the interrogator is enabled by a novel SRA quench frequency shift keying (SQ-FSK) based low data rate simplex communication. The SRTs are also designed to be roll invariant using bandwidth enhanced microstrip patch antennas. Theoretical analysis is done to derive expressions as a function of system parameters including the minimum SRA gain required for attaining a defined range and equations for the maximum number of symbols that can be transmitted in data transfer mode. Analysis of the dependency of quench pulse characteristics during data transfer shows that the duty cycle has to be varied while keeping the on-time constant to reduce ranging errors. Also the worsening of ranging precision at longer distances is predicted based on the non-idealities resulting from LFMCWchirp quantization due to SRT characteristics and is corroborated by system level measurements. In order to prove the system concept and study the semiconductor technology dependent factors, variants of 24GHz SRA ICs are designed in a 130nm silicon germanium (SiGe) bipolar complementary metal oxide technology (BiCMOS) and a partially depleted silicon on insulator (SOI) technology. Among the SRA ICs designed, the SiGe-BiCMOS ICs feature a novel quench pulse shaping concept to simultaneously improve the output power and minimum detectable input power. A direct antenna drive SRA IC based on a novel stacked transistor cross-coupled oscillator topology employing this concept exhibit one of the best reported combinations of minimum detected input power level of −100 dBm and output power level of 5.6 dBm, post wirebonding. The SiGe stacked transistor with base feedback capacitance topology employed in this design is analyzed to derive parameters including the SRA loop gain for design optimization. Other theoretical contributions include the analysis of the novel integrated quench pulse shaping circuit and formulas derived for output voltage swing taking bondwire losses into account. Another SiGe design variant is the buffered antenna drive SRA IC having a measured minimum detected input power level better than −80 dBm, and an output power level greater than 3.2 dBm after wirebonding. The two inputs and outputs of this IC also enables the design of roll invariant SRTs. Laboratory based ranging experiments done to test the concepts and theoretical considerations show a maximum measured distance of 77m while transferring data at the rate of 0.5 symbols per second using SQ-FSK. For distances less than 10m, the characterized accuracy is better than 11 cm and the precision is better than 2.4 cm. The combination of the maximum range, precision and accuracy are one of the best reported among similar works in literature to the author’s knowledge. In the 60GHz close range CW interrogator based system, the RF frontend transmits a continuous wave signal through the transmit path of a quasi circulator (QC) interfaced to an antenna to interrogate a PBT. The backscatter is received using the same antenna interfaced to the QC. The received signal is then amplified and downconverted for further processing. To prove this concept, two optimized QC ICs and a downconversion mixer IC are designed in a 22nm fully depleted SOI technology. The first QC is the transmission lines based QC which consumes a power of 5.4mW, operates at a frequency range from 56GHz to 64GHz and occupies an area of 0.49mm2. The transmit path loss is 5.7 dB, receive path gain is 2 dB and the tunable transmit path to receive path isolation is between 20 dB and 32 dB. The second QC is based on lumped elements, and operates in a relatively narrow bandwidth from 59.6GHz to 61.5GHz, has a gain of 8.5 dB and provides a tunable isolation better than 20 dB between the transmit and receive paths. This QC design also occupies a small area of 0.34mm² while consuming 13.2mW power. The downconversion is realized using a novel folded switching stage down conversion mixer (FSSDM) topology optimized to achieve one of the best reported combination of maximum voltage conversion gain of 21.5 dB, a factor of 2.5 higher than reported state-of-the-art results, and low power consumption of 5.25mW. The design also employs a unique back-gate tunable intermediate frequency output stage using which a gain tuning range of 5.5 dB is attained. Theoretical analysis of the FSSDM topology is performed and equations for the RF input stage transconductance, bandwidth, voltage conversion gain and gain tuning are derived. A feasibility study for the components of the 60GHz integrated single antenna interrogator frontend is also performed using PBTs to prove the system design concept.:1 Introduction 1 1.1 Motivation and Related Work . . . . . . . . . . . . . . . . . . . . . 1 1.2 Scope and Functional Specifications . . . . . . . . . . . . . . . . . 4 1.3 Objectives and Structure . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Features and Fundamentals of RFIDs and Superregenerative Amplifiers 9 2.1 RFID Transponder Technology . . . . . . . . . . . . . . . . . . . . 9 2.1.1 Chipless RFID Transponders . . . . . . . . . . . . . . . . . 10 2.1.2 Semiconductor based RFID Transponders . . . . . . . . . . 11 2.1.2.1 Passive Transponders . . . . . . . . . . . . . . . . 11 2.1.2.2 Active Transponders . . . . . . . . . . . . . . . . . 13 2.2 RFID Interrogator Architectures . . . . . . . . . . . . . . . . . . . 18 2.2.1 Interferometer based Interrogator . . . . . . . . . . . . . . . 19 2.2.2 Ultra-wideband Interrogator . . . . . . . . . . . . . . . . . . 20 2.2.3 Continuous Wave Interrogators . . . . . . . . . . . . . . . . 21 2.3 Coupling Dependent Range and Operating Frequencies . . . . . . . 25 2.4 RFID Ranging Techniques . . . . . . . . . . . . . . . . . . . . . . . 28 2.4.0.1 Received Signal Strength based Ranging . . . . . 28 2.4.0.2 Phase based Ranging . . . . . . . . . . . . . . . . 30 2.4.0.3 Time based Ranging . . . . . . . . . . . . . . . . . 30 2.5 Architecture Selection for Proof of Concept Systems . . . . . . . . 32 2.6 Superregenerative Amplifier (SRA) . . . . . . . . . . . . . . . . . . 35 2.6.1 Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . 42 2.6.3 Frequency Domain Characteristics . . . . . . . . . . . . . . 45 2.7 Semiconductor Technologies for RFIC Design . . . . . . . . . . . . 48 2.7.1 Silicon Germanium BiCMOS . . . . . . . . . . . . . . . . . 48 2.7.2 Silicon-on-Insulator . . . . . . . . . . . . . . . . . . . . . . . 48 3 24GHz Superregenerative Transponder based Identification and Rang- ing System 51 3.1 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.1 SRT Identification and Ranging . . . . . . . . . . . . . . . . 51 3.1.2 Power Link Analysis . . . . . . . . . . . . . . . . . . . . . . 55 3.1.3 Non-idealities . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.1.4 SRA Quench Frequency Shift Keying for data transfer . . . 61 3.1.5 Knowledge Gained . . . . . . . . . . . . . . . . . . . . . . . 63 3.2 RFIC Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.2.1 Low Power Direct Antenna Drive CMOS SRA IC . . . . . . 66 3.2.1.1 Circuit analysis and design . . . . . . . . . . . . . 66 3.2.1.2 Characterization . . . . . . . . . . . . . . . . . . . 69 3.2.2 Direct Antenna Drive SiGe SRA ICs . . . . . . . . . . . . . 71 3.2.2.1 Stacked Transistor Cross-coupled Quenchable Oscillator . . . . . . . . . . . . . . . . . . . . . . . . 72 3.2.2.1.1 Resonator . . . . . . . . . . . . . . . . . . 72 3.2.2.1.2 Output Network . . . . . . . . . . . . . . 75 3.2.2.1.3 Stacked Transistor Cross-coupled Pair and Loop Gain . . . . . . . . . . . . . . . . . 77 3.2.2.2 Quench Waveform Design . . . . . . . . . . . . . . 85 3.2.2.3 Characterization . . . . . . . . . . . . . . . . . . . 89 3.2.3 Antenna Diversity SiGe SRA IC with Integrated Quench Pulse Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.2.3.1 Circuit Analysis and Design . . . . . . . . . . . . 91 3.2.3.1.1 Crosscoupled Pair and Sampling Current 94 3.2.3.1.2 Common Base Input Stage . . . . . . . . 95 3.2.3.1.3 Cascode Output Stage . . . . . . . . . . . 96 3.2.3.1.4 Quench Pulse Shaping Circuit . . . . . . 96 3.2.3.1.5 Power Gain . . . . . . . . . . . . . . . . . 99 3.2.3.2 Characterization . . . . . . . . . . . . . . . . . . . 102 3.2.4 Knowledge Gained . . . . . . . . . . . . . . . . . . . . . . . 103 3.3 Proof of Principle System Implementation . . . . . . . . . . . . . . 106 3.3.1 Superregenerative Transponders . . . . . . . . . . . . . . . 106 3.3.1.1 Bandwidth Enhanced Microstrip Patch Antennas 108 3.3.2 FMCW Radar Interrogator . . . . . . . . . . . . . . . . . . 114 3.3.3 Chirp Z-transform Based Data Analysis . . . . . . . . . . . 116 4 60GHz Single Antenna RFID Interrogator based Identification System 121 4.1 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.2 RFIC Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.2.1 Quasi-circulator ICs . . . . . . . . . . . . . . . . . . . . . . 125 4.2.1.1 Transmission Lines based Quasi-Circulator IC . . 126 4.2.1.2 Lumped Elements WPD based Quasi-Circulator . 130 4.2.1.3 Characterization . . . . . . . . . . . . . . . . . . . 134 4.2.1.4 Knowledge Gained . . . . . . . . . . . . . . . . . . 135 4.2.2 Folded Switching Stage Downconversion Mixer IC . . . . . 138 4.2.2.1 FSSDM Circuit Design . . . . . . . . . . . . . . . 138 4.2.2.2 Cascode Transconductance Stage . . . . . . . . . . 138 4.2.2.3 Folded Switching Stage with LC DC Feed . . . . . 142 4.2.2.4 LO Balun . . . . . . . . . . . . . . . . . . . . . . . 145 4.2.2.5 Backgate Tunable IF Stage and Offset Correction 146 4.2.2.6 Voltage Conversion Gain . . . . . . . . . . . . . . 147 4.2.2.7 Characterization . . . . . . . . . . . . . . . . . . . 150 4.2.2.8 Knowledge Gained . . . . . . . . . . . . . . . . . . 151 4.3 Proof of Principle System Implementation . . . . . . . . . . . . . . 154 5 Experimental Tests 157 5.1 24GHz System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5.1.1 Ranging Experiments . . . . . . . . . . . . . . . . . . . . . 157 5.1.2 Roll Invariance Experiments . . . . . . . . . . . . . . . . . . 158 5.1.3 Joint Ranging and Data Transfer Experiments . . . . . . . 158 5.2 60GHz System Detection Experiments . . . . . . . . . . . . . . . . 165 6 Summary and Future Work 167 Appendices 171 A Derivation of Parameters for CB Amplifier with Base Feedback Capac- itance 173 B Definitions 177 C 24GHz Experiment Setups 179 D 60 GHz Experiment Setups 183 References 185 List of Original Publications 203 List of Abbreviations 207 List of Symbols 213 List of Figures 215 List of Tables 223 Curriculum Vitae 22

Low jitter phase-locked loop clock synthesis with wide locking range

The fast growing demand of wireless and high speed data communications has driven efforts to increase the levels of integration in many communications applications. Phase noise and timing jitter are important design considerations for these communications applications. The desire for highly complex levels of integration using low cost CMOS technologies works against the minimization of timing jitter and phase noise for communications systems which employ a phase-locked loop for frequency and clock synthesis with on-chip VCO. This dictates an integrated CMOS implementation of the VCO with very low phase noise performance. The ring oscillator VCOs based on differential delay cell chains have been used successfully in communications applications, but thermal noise induced phase noise have to be minimized in order not to limit their applicability to some applications which impose stringent timing jitter and phase noise requirements on the PLL clock synthesizer. Obtaining lower timing jitter and phase noise at the PLL output also requires the minimization of noise in critical circuit design blocks as well as the optimization of the loop bandwidth of the PLL. In this dissertation the fundamental performance limits of CMOS PLL clock synthesizers based on ring oscillator VCOs are investigated. The effect of flicker and thermal noise in MOS transistors on timing jitter and phase noise are explored, with particular emphasis on source coupled NMOS differential delay cells with symmetric load elements. Several new circuit architectures are employed for the charge pump circuit and phase-frequency detector (PFD) to minimize the timing jitter due to the finite dead zone in the PFD and the current mismatch in the charge pump circuit. The selection of the optimum PLL loop bandwidth is critical in determining the phase noise performance at the PLL output. The optimum loop bandwidth and the phase noise performance of the PLL is determined using behavioral simulations. These results are compared with transistor level simulated results and experimental results for the PLL clock synthesizer fabricated in a 0.35 µm CMOS technology with good agreement. To demonstrate the proposed concept, a fully integrated CMOS PLL clock synthesizer utilizing integer-N frequency multiplier technique to synthesize several clock signals in the range of 20-400 MHz with low phase noise was designed. Implemented in a standard 0.35-µm N-well CMOS process technology, the PLL achieves a period jitter of 6.5-ps (rms) and 38-ps (peak-to-peak) at 216 MHz with a phase noise of -120 dBc/Hz at frequency offsets above 10 KHz. The specific research contributions of this work include (1) proposing, designing, and implementing a new charge pump circuit architecture that matches current levels and therefore minimizes one source of phase noise due to fluctuations in the control voltage of the VCO, (2) an improved phase-frequency detector architecture which has improved characteristics in lock condition, (3) an improved ring oscillator VCO with excellent thermal noise induced phase noise characteristics, (4) the application of selfbiased techniques together with fixed bias to CMOS low phase noise PLL clock synthesizer for digital video communications ,and (5) an analytical model that describes the phase noise performance of the proposed VCO and PLL clock synthesizer

저 잡음 디지털 위상동기루프의 합성

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. 정덕균.As a device scaling proceeds, Charge Pump PLL has been confronted by many design challenges. Especially, a leakage current in loop filter and reduced dynamic range due to a lower operating voltage make it difficult to adopt a conventional analog PLL architecture for a highly scaled technology. To solve these issues, All Digital PLL (ADPLL) has been widely studied recently. ADPLL mitigates a filter leakage and a reduced dynamic range issues by replacing the analog circuits with digital ones. However, it is still difficult to get a low jitter under low supply voltage. In this thesis, we propose a dual loop architecture to achieve a low jitter even with a low supply voltage. And bottom-up based multi-step TDC and DCO are proposed to meet both fine resolution and wide operation range. In the aspect of design methodology, ADPLL has relied on a full custom design method although ADPLL is fully described in HDL (Hardware Description Language). We propose a new cell based layout technique to automatically synthesize the whole circuit and layout. The test chip has no linearity degradation although it is fully synthesized using a commercially available auto P&R tool. We has implemented an all digital pixel clock generator using the proposed dual loop architecture and the cell based layout technique. The entire circuit is automatically synthesized using 28nm CMOS technology. And s-domain linear model is utilized to optimize the jitter of the dual-loop PLL. Test chip occupies 0.032mm2, and achieves a 15ps_rms integrated jitter although it has extremely low input reference clock of 100 kHz. The whole circuit operates at 1.0V and consumes only 3.1mW.Abstract i Lists of Figures vii Lists of Tables xiii 1. Introduction 1 1.1 Thesis Motivation and Organization 1 1.1.1 Motivation 1 1.1.2 Thesis Organization 2 1.2 PLL Design Issues in Scaled CMOS Technology 3 1.2.1 Low Supply Voltage 4 1.2.2 High Leakage Current 6 1.2.3 Device Reliability: NBTI, HCI, TDDB, EM 8 1.2.4 Mismatch due to Proximity Effects: WPE, STI 11 1.3 Overview of Clock Synthesizers 14 1.3.1 Dual Voltage Charge Pump PLL 14 1.3.2 DLL Based Edge Combining Clock Multiplier 16 1.3.3 Recirculation DLL 17 1.3.4 Reference Injected PLL 18 1.3.5 All Digital PLL 19 1.3.6 Flying Adder Clock Synthesizer 20 1.3.7 Dual Loop Hybrid PLL 21 1.3.8 Comparisons 23 2. Tutorial of ADPLL Design 25 2.1 Introduction 25 2.1.1 Motivation for a pure digital 25 2.1.2 Conversion to digital domain 26 2.2 Functional Blocks 26 2.2.1 TDC, and PFD/Charge Pump 26 2.2.2 Digital Loop Filter and Analog R/C Loop Filter 29 2.2.3 DCO and VCO 34 2.2.4 S-domain Model of the Whole Loop 34 2.2.5 ADPLL Loop Design Flow 36 2.3 S-domain Noise Model 41 2.3.1 Noise Transfer Functions 41 2.3.2 Quantization Noise due to Limited TDC Resolution 45 2.3.3 Quantization Noise due to Divider ΔΣ Noise 46 2.3.4 Quantization Noise due to Limited DCO Resolution 47 2.3.5 Quantization Noise due to DCO ΔΣ Dithering 48 2.3.6 Random Noise of DCO and Input Clock 50 2.3.7 Over-all Phase Noise 50 3. Synthesizable All Digital Pixel Clock PLL Design 53 3.1 Overview 53 3.1.1 Introduction of Pixel Clock PLL 53 3.1.1 Design Specifications 55 3.2 Proposed Architecture 60 3.2.1 All Digital Dual Loop PLL 60 3.2.2 2-step controlled TDC 61 3.2.3 3-step controlled DCO 64 3.2.4 Digital Loop Filter 76 3.3 S-domain Noise Model 78 3.4 Loop Parameter Optimization Based on the s-domain Model 85 3.5 RTL and Gate Level Circuit Design 88 3.5.1 Overview of the design flow 88 3.5.2 Behavioral Simulation and Gate level synthesis 89 3.5.1 Preventing a meta-stability 90 3.5.1 Reusable Coding Style 92 3.6 Layout Synthesis 94 3.6.1 Auto P&R 94 3.6.2 Design of Unit Cells 97 3.6.3 Linearity Degradation in Synthesized TDC 98 3.6.4 Linearity Degradation in Synthesized DCO 106 3.7 Experiment Results 109 3.7.1 DCO measurement 109 3.7.2 PLL measurement 113 3.8 Conclusions 117 A. Device Technology Scaling Trends 118 A.1. Motivation for Technology Scaling 118 A.2. Constant Field Scaling 120 A.3. Quasi Constant Voltage Scaling 123 A.4. Device Technology Trends in Real World 124 B. Spice Simulation Tip for a DCO 137 C. Phase Noise to Jitter Conversion 141 Bibliography 144 초록 151Docto

Ultra-Low-Power Sensors and Receivers for IoT Applications

The combination of ultra-low power analog front-ends and CMOS-compatible transducers enable new applications, such as environmental monitors, household appliances, health trackers, etc. that are seamlessly integrated into our daily lives. Furthermore, wireless connectivity allows many of these sensors to operate both independently and collectively. These techniques collectively fulfil the recent surge of internet-of-things (IoT) applications that have the potential to fundamentally change daily life for millions of people.In this dissertation, the circuit and system design of wireless receivers and sensors is presented that explores the challenges of implementing long lifespan, high accuracy, and large coverage range IoT sensor networks. The first is a wake-up receiver (WuRX), which continuously monitors the RF environment to wake up a higher-power radio upon detection of a predetermined RF signature. This work both improves sensitivity and reduces power over prior art through a multi-faceted design featuring an impedance transformation network with large passive voltage gain, an active envelope detector with high input impedance to facilitate large passive voltage gain, a low-power precision comparator, and a low-leakage digital baseband correlator.Although pushing the prior WuRX performance boundary by orders of magnitude, the first work shows moderate sensitivity, inferior temperature robustness, and large area with external lumped components. Thus, the second work shows a miniaturized WuRX that is temperature-compensated, yet still consumes only nano-watt power and millimeter area while operating at 9 GHz. To further reduce the area, a global common-mode feedback is utilized across the envelope detector and baseband amplifier that eliminates the need for off-chip ac-coupling components. Multiple temperature-compensation techniques are proposed to maintain constant bandwidth of the signal path and constant clock frequency. Both WuRXs operate at 0.4 V supply, consume near-zero power and achieve ~-70 dBm sensitivity.Lastly, the first reported CMOS 2-in-1 relative humidity and temperature sensor is presented. A unified analog front-end interfaces on-chip transducers and converts the inputs into a frequency vis a high-linearity frequency-locked loop. An incomplete-settling switched-capacitor-based Wheatstone bridge is proposed to sense the inputs in a power-efficient fashion

Analysis and design of wideband voltage controlled oscillators using self-oscillating active inductors.

Voltage controlled oscillators (VCOs) are essential components of RF circuits used in transmitters and receivers as sources of carrier waves with variable frequencies. This, together with a rapid development of microelectronic circuits, led to an extensive research on integrated implementations of the oscillator circuits. One of the known approaches to oscillator design employs resonators with active inductors electronic circuits simulating the behavior of passive inductors using only transistors and capacitors. Such resonators occupy only a fraction of the silicon area necessary for a passive inductor, and thus allow to use chip area more eectively. The downsides of the active inductor approach include: power consumption and noise introduced by transistors. This thesis presents a new approach to active inductor oscillator design using selfoscillating active inductor circuits. The instability necessary to start oscillations is provided by the use of a passive RC network rather than a power consuming external circuit employed in the standard oscillator approach. As a result, total power consumption of the oscillator is improved. Although, some of the active inductors with RC circuits has been reported in the literature, there has been no attempt to utilise this technique in wideband voltage controlled oscillator design. For this reason, the dissertation presents a thorough investigation of self-oscillating active inductor circuits, providing a new set of design rules and related trade-os. This includes: a complete small signal model of the oscillator, sensitivity analysis, large signal behavior of the circuit and phase noise model. The presented theory is conrmed by extensive simulations of wideband CMOS VCO circuit for various temperatures and process variations. The obtained results prove that active inductor oscillator performance is obtained without the use of standard active compensation circuits. Finally, the concept of self-oscillating active inductor has been employed to simple and fast OOK (On-Off Keying) transmitter showing energy eciency comparable to the state of the art implementations reported in the literature

Collective analog bioelectronic computation

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student submitted PDF version of thesis.Includes bibliographical references (p. 677-710).In this thesis, I present two examples of fast-and-highly-parallel analog computation inspired by architectures in biology. The first example, an RF cochlea, maps the partial differential equations that describe fluid-membrane-hair-cell wave propagation in the biological cochlea to an equivalent inductor-capacitor-transistor integrated circuit. It allows ultra-broadband spectrum analysis of RF signals to be performed in a rapid low-power fashion, thus enabling applications for universal or software radio. The second example exploits detailed similarities between the equations that describe chemical-reaction dynamics and the equations that describe subthreshold current flow in transistors to create fast-and-highly-parallel integrated-circuit models of protein-protein and gene-protein networks inside a cell. Due to a natural mapping between the Poisson statistics of molecular flows in a chemical reaction and Poisson statistics of electronic current flow in a transistor, stochastic effects are automatically incorporated into the circuit architecture, allowing highly computationally intensive stochastic simulations of large-scale biochemical reaction networks to be performed rapidly. I show that the exponentially tapered transmission-line architecture of the mammalian cochlea performs constant-fractional-bandwidth spectrum analysis with O(N) expenditure of both analysis time and hardware, where N is the number of analyzed frequency bins. This is the best known performance of any spectrum-analysis architecture, including the constant-resolution Fast Fourier Transform (FFT), which scales as O(N logN), or a constant-fractional-bandwidth filterbank, which scales as O (N2).(cont.) The RF cochlea uses this bio-inspired architecture to perform real-time, on-chip spectrum analysis at radio frequencies. I demonstrate two cochlea chips, implemented in standard 0.13m CMOS technology, that decompose the RF spectrum from 600MHz to 8GHz into 50 log-spaced channels, consume < 300mW of power, and possess 70dB of dynamic range. The real-time spectrum analysis capabilities of my chips make them uniquely suitable for ultra-broadband universal or software radio receivers of the future. I show that the protein-protein and gene-protein chips that I have built are particularly suitable for simulation, parameter discovery and sensitivity analysis of interaction networks in cell biology, such as signaling, metabolic, and gene regulation pathways. Importantly, the chips carry out massively parallel computations, resulting in simulation times that are independent of model complexity, i.e., O(1). They also automatically model stochastic effects, which are of importance in many biological systems, but are numerically stiff and simulate slowly on digital computers. Currently, non-fundamental data-acquisition limitations show that my proof-of-concept chips simulate small-scale biochemical reaction networks at least 100 times faster than modern desktop machines. It should be possible to get 103 to 106 simulation speedups of genome-scale and organ-scale intracellular and extracellular biochemical reaction networks with improved versions of my chips. Such chips could be important both as analysis tools in systems biology and design tools in synthetic biology.by Soumyajit Mandal.Ph.D