Techniques for Frequency Synthesizer-Based Transmitters.

Internet of Things (IoT) devices are poised to be the largest market for the semiconductor industry. At the heart of a wireless IoT module is the radio and integral to any radio is the transmitter. Transmitters with low power consumption and small area are crucial to the ubiquity of IoT devices. The fairly simple modulation schemes used in IoT systems makes frequency synthesizer-based (also known as PLL-based) transmitters an ideal candidate for these devices. Because of the reduced number of analog blocks and the simple architecture, PLL-based transmitters lend themselves nicely to the highly integrated, low voltage nanometer digital CMOS processes of today. This thesis outlines techniques that not only reduce the power consumption and area, but also significantly improve the performance of PLL-based transmitters.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/113385/1/mammad_1.pd

Techniques for Wideband All Digital Polar Transmission

abstract: Modern Communication systems are progressively moving towards all-digital transmitters (ADTs) due to their high efficiency and potentially large frequency range. While significant work has been done on individual blocks within the ADT, there are few to no full systems designs at this point in time. The goal of this work is to provide a set of multiple novel block architectures which will allow for greater cohesion between the various ADT blocks. Furthermore, the design of these architectures are expected to focus on the practicalities of system design, such as regulatory compliance, which here to date has largely been neglected by the academic community. Amongst these techniques are a novel upconverted phase modulation, polyphase harmonic cancellation, and process voltage and temperature (PVT) invariant Delta Sigma phase interpolation. It will be shown in this work that the implementation of the aforementioned architectures allows ADTs to be designed with state of the art size, power, and accuracy levels, all while maintaining PVT insensitivity. Due to the significant performance enhancement over previously published works, this work presents the first feasible ADT architecture suitable for widespread commercial deployment.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Low-Power High-Data-Rate Transmitter Design for Biomedical Application

Ph.DDOCTOR OF PHILOSOPH

45-nm SOI CMOS Bluetooth Electrochemical Sensor for Continuous Glucose Monitoring

Due to increasing rates of diabetes, non-invasive glucose monitoring systems will become critical to improving health outcomes for an increasing patient population. Bluetooth integration for such a system has been previously unattainable due to the prohibitive energy consumption. However, enabling Bluetooth allows for widespread adoption due to the ubiquity of Bluetooth-enabled mobile devices. The objective of this thesis is to demonstrate the feasibility of a Bluetooth-based energy-harvesting glucose sensor for contact-lens integration using 45~nm silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology. The proposed glucose monitoring system includes a Bluetooth transmitter implemented as a two-point closed loop PLL modulator, a sensor potentiostat, and a 1st-order incremental delta-sigma analog-to-digital converter (IADC). This work details the complete system design including derivation of top-level specifications such as glucose sensing range, Bluetooth protocol timing, energy consumption, and circuit specifications such as carrier frequency range, output power, phase-noise performance, stability, resolution, signal-to-noise ratio, and power consumption. Three test chips were designed to prototype the system, and two of these were experimentally verified. Chip 1 includes a partial implementation of a phase-locked-loop (PLL) which includes a voltage-controlled-oscillator (VCO), frequency divider, and phase-frequency detector (PFD). Chip 2 includes the design of the sensor potentiostat and IADC. Finally, Chip 3 combines the circuitry of Chip 1 and Chip 2, along with a charge-pump, loop-filter and power amplifier to complete the system. Chip 1 DC power consumption was measured to be 204.8~$\mu$W, while oscillating at 2.441 GHz with an output power $P_{out}$ of -35.8 dBm, phase noise at 1 MHz offset $L(1\text{ MHz})$ of -108.5 dBc/Hz, and an oscillator figure of merit (FOM) of 183.44dB. Chip 2 achieves a total DC power consumption of 5.75~$\mu$W. The system has a dynamic range of 0.15~nA -- 100~nA at 10-bit resolution. The integral non-linearity (INL) and differential non-linearity (DNL) of the IADC were measured to be -6~LSB/$\pm$0.3~LSB respectively with a conversion time of 65.56~ms. This work achieves the best duty-cycled DC power consumption compared to similar glucose monitoring systems, while providing sufficient performance and range using Bluetooth

Low phase noise, high bandwidth frequency synthesis techniques

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 243-249).A quantization noise reduction technique is proposed that allows fractional-N frequency synthesizers to achieve high closed loop bandwidth and low output phase noise simultaneously. Quantization induced phase noise is the bottleneck in state-of-the-art synthesizer design, and results in a noise-bandwidth tradeoff that typically limits closed loop synthesizer bandwidths to be <100kHz for adequate phase noise performance to be achieved. Using the proposed technique, quantization noise is reduced to the point where intrinsic noise sources (VCO, charge-pump, reference and PFD noise) ultimately limit noise performance. An analytical model that draws an analogy between fractional-N frequency synthesizers and MASH A digital-to-analog converters is proposed. Calculated performance of a synthesizer implementing the proposed quantization noise reduction techniques shows excellent agreement with simulation results of a behavioral model. Behavioral modeling techniques that progressively incorporate non-ideal circuit behavior based on SPICE level simulations are proposed. The critical circuits used to build the proposed synthesizer are presented.(cont.) These include a divider retiming circuit that avoids meta-stability related to synchronizing an asynchronous signal, a timing mismatch compensation block used by a dual divider path PFD, and a unit element current source design for reduced output phase noise. Measurement results of a prototype 0.18/m CMOS synthesizer show that quantization noise is suppressed by 29dB when the proposed synthesizer architecture is compared to 2nd order EA frequency synthesizer. The 1MHz closed loop bandwidth allows the synthesizer to be modulated by up to 1Mb/s GMSK data for use as a transmitter with 1.8GHz and 900MHz outputs. The analytical model is used to back extract on-chip mismatch parameters that are not directly measurable. This represents a new analysis technique that is useful in the characterization of fractional-N frequency synthesizers.by Scott Edward Meninger.Ph.D

Optimised soft-core processor architecture for noise jamming

M.Ing. (Electrical & Electronic Engineering)Abstract: Noise jamming is a traditional electronic counter measure (ECM) that existed since the establishment of electronic warfare (EW). Traditional noise jamming techniques have been shown to be failing when interacting with intelligent Radar systems such as pulse Doppler radar. Hence there is a need to introduce new noise jamming techniques with digital architecture that will provide improved performance against smart pulse Doppler radar. The work is undertaken to investigate the feasibility of digitizing noise jamming. It focuses on analog-to-digital conversion optimization towards noise jamming architecture, as a result digitization will allow for an opportunity for adaptation of intelligent processing that previously didn’t exist. In this dissertation, certain contributions to the field of noise jamming were made by introducing state of the art odd/even order sampling architecture by proving four case studies. Case study 1 experimentally investigates sample frequency behaviour. Case study 2 uses simulation to investigate step-size and dynamic range behaviour. Case study 3 uses FPGA implementation and SNR to investigate quantization error behaviour. Case study 3 also uses SNR to investigate superiority of proposed odd/even order sampling. Lastly case study 4 uses field measurements, FPGA implementation and SNR to investigate practical implementation of digitized noise jamming. The main contribution is concerned with an architecture that digitizes, reduces sample frequency, optimizes digital resource utilization while reducing noise jamming signal-to-noise ratio. The approach evaluates and empirically compares three sampling techniques from lecture Mod-Δ, Mod-Δ (Gaussian) and Mod-Δ (Sinusoidal) with proposed novel odd/even order sampling. Sampling techniques are evaluated in terms of quantization error, mean square error and signal-to-noise ratio. It was found that the proposed novel odd/even order sampling achieved most case SNR performance of 6 dB in comparison to 18 dB for Mod-Δ. Sampling frequency findings indicated that the proposed novel odd/even order sampling had achieved sampling frequency of 2 kHz in comparison to 8 kHz from traditional 1st order sigma-delta. Dynamic range findings indicated that the proposed odd/even order sampling achieved a dynamic range of 1.088 volts/ms in comparison to 1.185 volts/ms from traditional 1st order sigma-delta. Findings have indicated that the proposed odd/even order sampling has superior SNR and sampling frequency..

Proceedings of the Second International Mobile Satellite Conference (IMSC 1990)

Presented here are the proceedings of the Second International Mobile Satellite Conference (IMSC), held June 17-20, 1990 in Ottawa, Canada. Topics covered include future mobile satellite communications concepts, aeronautical applications, modulation and coding, propagation and experimental systems, mobile terminal equipment, network architecture and control, regulatory and policy considerations, vehicle antennas, and speech compression

Telecommunications system of a CubeSat satellite

This Final degree's thesis is done under the UPC-Canadà program in which the author realizes his last degree year in Montréal, Canada, to the Polytechnique de Montréal university under the supervision of Dr. Giovanni Beltrame being part of his laboratory Mistlab and also on the Polyorbite group of students. Polyorbite is an organization that participates in the biannual contest CSDC (Canadian Satellite Design Challenge) that consists on the realization from 0 of a 3U CubeSat by undergraduate and master students. By the start of this thesis on September 2016, the contest was in the middle of the 2014-2016 iteration without having almost nothing on the telecommunication part, having just 2 semesters for design, build and test an entirely telecommunications system, suitable for the satellite purpose, until June 2016 in which the final presentations of the contest took place on Ottawa. The purpose of this thesis is then an early design of a telecommunications system for a CubeSat satellite

The Telecommunications and Data Acquisition Report

Archival reports are given on developments in programs managed by JPL's Office of Telecommunications and Data Acquisition (TDA), including space communications, radio navigation, radio science, ground-based radio and radar astronomy, and the Deep Space Network (DSN) and its associated Ground Communications Facility (GCF) in planning, supporting research and technology, implementation, and operations. Also included is TDA-funded activity at JPL on data and information systems and reimbursable DSN work performed for other space agencies through NASA. In the search for extraterrestrial intelligence (SETI), implementation and operations for searching the microwave spectrum are reported. Use of the Goldstone Solar System Radar for scientific exploration of the planets, their rings and satellites, asteroids, and comets are discussed