전원 잡음에 둔감한 고리 발진기와 디지털 위상 동기 회로 설계

학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2023. 2. 정덕균.One of the critical blocks integrated into the PAM4-binary bridge, bridging the high-speed DRAM and the low-speed DRAM Tester, is an All-Digital Phase-Locked Loop (ADPLL). Since the transmitter and receiver operate based on the clock signal, whose frequency is doubled compared to the clock signal transmitted from the memory tester by the ADPLL, the ADPLL needs to have a low RMS jitter and high Process-Voltage-Temperature (PVT) tolerance characteristics. However, due to the complex bridge circuit sharing the supply power with the ADPLL, power supply noise (PSN) is the main challenge for the Ring Oscillator (RO) based ADPLL. This thesis presents a Supply Noise-Insensitive RO-based ADPLL. A supply noise absorbing shunt regulator composed of 31-bit NMOS transistors Array is embedded parallel to the RO. Output codes from the Digital Loop Filter (DLF) not only control the Digitally-Controlled Resistor (DCR) but also the transconductance of the NMOS transistor Array. The proposed ADPLL is fabricated in the 40-nm CMOS technology. The ADPLL occupies an active area of 0.06 mm2 and consumes power 13.5 mW, while the proposed scheme only takes 6.6% and 2.8% of it, respectively. At 8 GHz operation, the proposed ADPLL achieves an RMS jitter of 3.255 ps with 1-MHz 40-mVpp sinusoidal noise injected into the supply voltage. With the Supply Noise-Insensitive technique, the RMS jitter lowers to 1.268 ps.고속 DRAM과 저속 검사 장비를 연결하는 4단계 펄스 진폭 변조-2진법 브리지 칩의 주요 구성 회로 중에 디지털 위상 동기 회로가 있다. 이 회로가 검사 장비에서 온 참조 클락의 진동수를 2배로 빠르게 하여 출력하고, 그 클락을 기준으로 칩의 송수신 회로들이 동작하기 때문에 낮은 RMS 지터와 공정-전압-온도 변화에 둔감한 성능이 요구된다. 하지만, 칩의 복잡한 회로들 때문에 고리 발진기를 기반으로 한 이 회로에게 전원 전압 잡음이 가장 큰 문제점이 된다. 본 논문은 전원 잡음에 둔감한 고리 발진기를 기반으로 한 디지털 위상 동기 회로를 제안한다. 전원 잡음을 흡수하는 단락 레귤레이터 역할의 31-비트NMOS 트랜지스터 배열이 고리 발진기와 평행하게 구현되었다. 디지털 제어 저항을 조절하는 디지털 루프 필터에서 온 행 조정 비트들이 NMOS 트랜지스터 배열의 트랜스컨덕턴스도 조절하게 디자인하였다. 제안된 디지털 위상 동기 회로는 40-nm CMOS 공정으로 제작되었다. 0.06 mm2 의 면적을 차지하고 13.5 mW의 전력을 소모하며, 고안된 전원 잡음 흡수 회로는 각각 0.0017 mm2와 0.9mW, 즉, 전체의 6.6%와 2.8%만 차지하였다. 8GHz 동작에서, 제안된 회로는 1-MHz 40-mVpp 사인파 전원 잡음 아래에서 3.255 ps의 RMS 지터를 보였지만, 고안된 회로의 동작과 함께 1.268 ps로 줄었다.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 4 CHAPTER 2 BACKGROUNDS 5 2.1 OVERVIEW 5 2.2 COMPOSITIONS OF THE ADPLL 8 2.2.1 TIME-TO-DIGITAL CONVERTER 8 2.2.2 DIGITAL LOOP FILTER 11 2.2.3 DIGITALLY CONTROLLED OSCILLATOR 14 2.2.4 PRIOR WORKS OF SUPPLY NOISE CANCELLATION 19 2.3 ADPLL LOOP ANALYSIS 21 2.3.1 LOOP TRANSFER FUNCTION 21 2.3.2 NOISE MODELING 23 CHAPTER 3 DESIGN OF SUPPLY NOISE-INSENSITIVE ADPLL 26 3.1 DESIGN CONSIDERATION 26 3.2 OVERALL ARCHITECTURE 28 3.3 PROPOSED CIRCUIT IMPLEMENTATION 30 3.3.1 PFD-TDC AND DIGITAL BLOCK 30 3.3.2 PROPOSED DCO WITH DCR 33 3.3.3 NMOS SHUNT REGULATOR ARRAY 37 3.3.4 SUPPLY SENSING AMPLIFIER 39 3.3.5 SUPPLY NOISE-INSENSITIVE TECHNIQUE 41 CHAPTER 4 MEASUREMENT RESULTS 43 4.1 CHIP PHOTOMICROGRAPH 43 4.2 MEASUREMENT SETUP 45 4.3 MEASUREMENT RESULTS 46 4.3.1 FREE-RUNNING DCO 46 4.3.2 CLOSED-LOOP PERFORMANCE 47 4.4 PERFORMANCE SUMMARY 49 CHAPTER 5 CONCLUSION 51 BIBLIOGRAPHY 52 초 록 55석

A Low-Power Silicon-Photomultiplier Readout ASIC for the CALICE Analog Hadronic Calorimeter

The future e + e − collider experiments, such as the international linear collider, provide precise measurements of the heavy bosons and serve as excellent tests of the underlying fundamental physics. To reconstruct these bosons with an unprecedented resolution from their multi-jet final states, a detector system employing the particle flow approach has been proposed, requesting calorimeters with imaging capabilities. The analog hadron calorimeter based on the SiPM-on-tile technology is one of the highly granular candidates of the imaging calorimeters. To achieve the compactness, the silicon-photomultiplier (SiPM) readout electronics require a low-power monolithic solution. This thesis presents the design of such an application-specific integrated circuit (ASIC) for the charge and timing readout of the SiPMs. The ASIC provides precise charge measurement over a large dynamic range with auto-triggering and local zero-suppression functionalities. The charge and timing information are digitized using channel-wise analog-to-digital and time-to-digital converters, providing a fully integrated solution for the SiPM readout. Dedicated to the analog hadron calorimeter, the power-pulsing technique is applied to the full chip to meet the stringent power consumption requirement. This work also initializes the commissioning of the calorimeter layer with the use of the designed ASIC. An automatic calibration procedure has been developed to optimized the configuration settings for the chip. The new calorimeter base unit with the designed ASIC has been produced and its functionality has been tested

차량용 CIS Interface 를 위한 All-Digital Phase-Locked Loop 의 설계 및 분석

학위논문 (석사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2021. 2. 정덕균.This thesis presents design techniques for All-Digital Phase-Locked Loop (ADPLL) assisting the automotive CMOS image sensor (CIS) interface. To target Gear 3 of the automotive physical system, the proposed AD-PLL has a wide operation range, low RMS jitter, and high PVT tolerance characteristics. Detailed analysis of the loop dynamics and the noise analysis of AD-PLL are done by using Matlab and Verilog behavioral modeling simulation before an actual design. Based on that analysis, the optimal DLF gain configurations are yielded, and also, accurate output responses and performance are predictable. The design techniques to reduce the output RMS jitter are discussed thoroughly and utilized for actual implementation. The proposed AD-PLL is fabricated in the 40 nm CMOS process and occupies an effective area of 0.026 mm2. The PLL output clock pulses exhibit an RMS jitter of 827 fs at 2 GHz. The power dissipation is 5.8 mW at 2 GHz, where the overall supply voltage domain is 0.9 V excluding the buffer which is 1.1 V domain.본 논문에서는 자동차 CMOS 이미지 센서 (CIS) 인터페이스를 지원하 는 AD-PLL 을 제안한다. Automotive Physical 시스템의 Gear 3 를 지원하기 위해 제안된 AD-PLL 은 1.5 GHz 에서 3 GHz 의 동작 주파수를 가지며, 낮 은 RMS Jitter 및 PVT 변화에 대한 높은 둔감성을 갖는다. 설계에 앞서서 Matlab 및 Verilog Behavioral Simulation 을 통해 Loop system 의 역학에 대한 자세한 분석 및 AD-PLL 의 Noise 분석을 수행하였고, 이 분석을 기반으로 최적의 DLF gain 과 정확한 출력 응답 및 성능을 예측 할 수 있었다. 또한, 출력의 Phase Noise 와 RMS Jitter 를 줄이기 위한 설계 기법을 자세히 다루고 있으며 이를 실제 구현에 활용했다. 제안된 회로는 40 nm CMOS 공정으로 제작되었으며 Decoupling Cap 을 제외하고 0.026 mm2 의 유효 면적을 차지한다. 측정된 출력 Clock 신호의 RMS Jitter 값은 2 GHz 에서 827 fs 이며, 총 5.8 mW의 Power 를 소비한다. 이 때, 전체적인 공급 전압은 0.9 V 이며, Buffer 의 Power 만이 1.1 V 를 사용하 였다.ABSTRACT I CONTENTS II LIST OF FIGURES IV LIST OF TABLES VII CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2 BACKGROUND ON ALL-DIGITAL PLL 4 2.1 OVERVIEW 4 2.2 BUILDING BLOCKS OF AD-PLL 7 2.2.1 TIME-TO-DIGITAL CONVERTER 7 2.2.2 DIGITALLY-CONTROLLED OSCILLATOR 10 2.2.3 DIGITAL LOOP FILTER 13 2.2.4 DELTA-SIGMA MODULATOR 16 2.3 PHASE NOISE ANALYSIS OF AD-PLL 20 2.3.1 BASIC ASSUMPTION OF LINEAR ANALYSIS 20 2.3.2 NOISE SOURCES OF AD-PLL 21 2.3.3 EFFECTS OF LOOP DELAY ON AD-PLL 24 2.3.4 PHASE NOISE ANALYSIS OF PROPOSED AD-PLL 26 CHAPTER 3 DESIGN OF ALL-DIGITAL PLL 28 3.1 DESIGN CONSIDERATION 28 3.2 OVERALL ARCHITECTURE 30 3.3 CIRCUIT IMPLEMENTATION 32 3.3.1 PFD-TDC 32 3.3.2 DCO 37 3.3.3 DIGITAL BLOCK 43 3.3.4 LEVEL SHIFTING BUFFER AND DIVIDER 45 CHAPTER 4 MEASUREMENT AND SIMULATION RESULTS 52 4.1 DIE PHOTOMICROGRAPH 52 4.2 MEASUREMENT SETUP 54 4.3 TRANSIENT ANALYSIS 57 4.4 PHASE NOISE AND SPUR PERFORMANCE 59 4.4.1 FREE-RUNNING DCO 59 4.4.2 PLL PERFORMANCE 61 4.5 PERFORMANCE SUMMARY 65 CHAPTER 5 CONCLUSION 67 BIBLIOGRAPHY 68 초 록 72Maste

RF MEMS reference oscillators platform for wireless communications

A complete platform for RF MEMS reference oscillator is built to replace bulky quartz from mobile devices, thus reducing size and cost. The design targets LTE transceivers. A low phase noise 76.8 MHz reference oscillator is designed using material temperature compensated AlN-on-silicon resonator. The thesis proposes a system combining piezoelectric resonator with low loading CMOS cross coupled series resonance oscillator to reach state-of-the-art LTE phase noise specifications. The designed resonator is a two port fundamental width extensional mode resonator. The resonator characterized by high unloaded quality factor in vacuum is designed with low temperature coefficient of frequency (TCF) using as compensation material which enhances the TCF from - 3000 ppm to 105 ppm across temperature ranges of -40˚C to 85˚C. By using a series resonant CMOS oscillator, phase noise of -123 dBc/Hz at 1 kHz, and -162 dBc/Hz at 1MHz offset is achieved. The oscillator’s integrated RMS jitter is 106 fs (10 kHz–20 MHz), consuming 850 μA, with startup time is 250μs, achieving a Figure-of-merit (FOM) of 216 dB. Electronic frequency compensation is presented to further enhance the frequency stability of the oscillator. Initial frequency offset of 8000 ppm and temperature drift errors are combined and further addressed electronically. A simple digital compensation circuitry generates a compensation word as an input to 21 bit MASH 1 -1-1 sigma delta modulator incorporated in RF LTE fractional N-PLL for frequency compensation. Temperature is sensed using low power BJT band-gap front end circuitry with 12 bit temperature to digital converter characterized by a resolution of 0.075˚C. The smart temperature sensor consumes only 4.6 μA. 700 MHz band LTE signal proved to have the stringent phase noise and frequency resolution specifications among all LTE bands. For this band, the achieved jitter value is 1.29 ps and the output frequency stability is 0.5 ppm over temperature ranges from -40˚C to 85˚C. The system is built on 32nm CMOS technology using 1.8V IO device

Synchronising coherent networked radar using low-cost GPS-disciplined oscillators

This text evaluates the feasibility of synchronising coherent, pulsed-Doppler, networked, radars with carrier frequencies of a few gigahertz and moderate bandwidths of tens of megahertz across short baselines of a few kilometres using low-cost quartz GPSDOs based on one-way GPS time transfer. It further assesses the use of line-of-sight (LOS) phase compensation, where the direct sidelobe breakthrough is used as the phase reference, to improve the GPS-disciplined oscillator (GPSDO) synchronised bistatic Doppler performance. Coherent bistatic, multistatic, and networked radars require accurate time, frequency, and phase synchronisation. Global positioning system (GPS) synchronisation is precise, low-cost, passive and covert, and appears well-suited to synchronise networked radar. However, very few published examples exist. An imperfectly synchronised bistatic transmitter-receiver is modelled. Measures and plots are developed enabling the rapid selection of appropriate synchronisation technologies. Three low-cost, open, versatile, and extensible, quartz-based GPSDOs are designed and calibrated at zero-baselines. These GPSDOs are uniquely capable of acquiring phase-lock four times faster than conventional phase-locked loops (PLLs) and a new time synchronisation mechanism enables low-jitter sub-10 ns oneway GPS time synchronisation. In collaboration with University College London, UK, the 2.4 GHz coherent pulsed-Doppler networked radar, called NetRAD, is synchronised using the University of Cape Town developed GPSDOs. This resulted in the first published example of pulsed-Doppler phase synchronisation using GPS. A tri-static experiment is set up in Simon’s Bay, South Africa, with a maximum baseline of 2.3 km. The Roman Rock lighthouse was used as a static target to simultaneously assess the range, frequency, phase, and Doppler performance of the monostatic, bistatic, and LOS phase corrected bistatic returns. The real-world results compare well to that predicted by the earlier developed bistatic model and zero-baseline calibrations. GPS timing limits the radar bandwidth to less than 37.5 MHz when it is required to synchronise to within the range resolution. Low-cost quartz GPSDOs offer adequate frequency synchronisation to ensure a target radial velocity accuracy of better than 1 km/h and frequency drift of less than the Doppler resolution over integration periods of one second or less. LOS phase compensation, when used in combination with low-cost GPSDOs, results in near monostatic pulsed-Doppler performance with a subclutter visibility improvement of about 30 dB

A high speed serializer/deserializer design

A Serializer/Deserializer (SerDes) is a circuit that converts parallel data into a serial stream and vice versa. It helps solve clock/data skew problems, simplifies data transmission, lowers the power consumption and reduces the chip cost. The goal of this project was to solve the challenges in high speed SerDes design, which included the low jitter design, wide bandwidth design and low power design. A quarter-rate multiplexer/demultiplexer (MUX/DEMUX) was implemented. This quarter-rate structure decreases the required clock frequency from one half to one quarter of the data rate. It is shown that this significantly relaxes the design of the VCO at high speed and achieves lower power consumption. A novel multi-phase LC-ring oscillator was developed to supply a low noise clock to the SerDes. This proposed VCO combined an LC-tank with a ring structure to achieve both wide tuning range (11%) and low phase noise (-110dBc/Hz at 1MHz offset). With this structure, a data rate of 36 Gb/s was realized with a measured peak-to-peak jitter of 10ps using 0.18microm SiGe BiCMOS technology. The power consumption is 3.6W with 3.4V power supply voltage. At a 60 Gb/s data rate the simulated peak-to-peak jitter was 4.8ps using 65nm CMOS technology. The power consumption is 92mW with 2V power supply voltage. A time-to-digital (TDC) calibration circuit was designed to compensate for the phase mismatches among the multiple phases of the PLL clock using a three dimensional fully depleted silicon on insulator (3D FDSOI) CMOS process. The 3D process separated the analog PLL portion from the digital calibration portion into different tiers. This eliminated the noise coupling through the common substrate in the 2D process. Mismatches caused by the vertical tier-to-tier interconnections and the temperature influence in the 3D process were attenuated by the proposed calibration circuit. The design strategy and circuits developed from this dissertation provide significant benefit to both wired and wireless applications

Formal Verification and In-Situ Test of Analog and Mixed-Signal Circuits

As CMOS technologies continuously scale down, designing robust analog and mixed-signal (AMS) circuits becomes increasingly difficult. Consequently, there are pressing needs for AMS design checking techniques, more specifically design verification and design for testability (DfT). The purpose of verification is to ensure that the performance of an AMS design meets its specification under process, voltage and temperature (PVT) variations and different working conditions, while DfT techniques aim at embedding testability into the design, by adding auxiliary circuitries for testing purpose. This dissertation focuses on improving the robustness of AMS designs in highly scaled technologies, by developing novel formal verification and in-situ test techniques. Compared with conventional AMS verification that relies more on heuristically chosen simulations, formal verification provides a mathematically rigorous way of checking the target design property. A formal verification framework is proposed that incorporates nonlinear SMT solving techniques and simulation exploration to efficiently verify the dynamic properties of AMS designs. A powerful Bayesian inference based technique is applied to dynamically tradeoff between the costs of simulation and nonlinear SMT. The feasibility and efficacy of the proposed methodology are demonstrated on the verification of lock time specification of a charge-pump PLL. The powerful and low-cost digital processing capabilities of today?s CMOS technologies are enabling many new in-situ test schemes in a mixed-signal environment. First, a novel two-level structure of GRO-PVDL is proposed for on-chip jitter testing of high-speed high-resolution applications with a gated ring oscillator (GRO) at the first level to provide a coarse measurement and a Vernier-style structure at the second level to further measure the residue from the first level with a fine resolution. With the feature of quantization noise shaping, an effective resolution of 0.8ps can be achieved using a 90nm CMOS technology. Second, the reconfigurability of recent all-digital PLL designs is exploited to provide in-situ output jitter test and diagnosis abilities under multiple parametric variations of key analog building blocks. As an extension, an in-situ test scheme is proposed to provide online testing for all-digital PLL based polar transmitters

A PLL based built-in self-test for MEMS sensors

A new readout circuit for capacitive Micro-Electrical-Mechanical System (MEMS) devices has been proposed, developed and simulated in this thesis. The readout circuit utilizes a Phase Locked Loop (PLL) to convert variations of MEM capacitance to time domain signals. The proposed circuit demonstrates a robust performance against process, power supply and temperature variations due to inherent feedback of PLL systems. Post layout simulation results in Cadence environment using TSMC CMOS 65nm technology indicate that the implemented readout circuit can successfully measure and detect minor variations of MEMS capacitance from its nominal value

Online Timing Slack Measurement and its Application in Field-Programmable Gate Arrays

Reliability, power consumption and timing performance are key concerns for today's integrated circuits. Measurement techniques capable of quantifying the timing characteristics of a circuit, while it is operating, facilitate a range of benefits. Delay variation due to environmental and operational conditions, and degradation can be monitored by tracking changes in timing performance. Using the measurements in a closed-loop to control power supply voltage or clock frequency allows for the reduction of timing safety margins, leading to improvements in power consumption or throughput performance through the exploitation of better-than worst-case operation. This thesis describes a novel online timing slack measurement method which can directly measure the timing performance of a circuit, accurately and with minimal overhead. Enhancements allow for the improvement of absolute accuracy and resolution. A compilation flow is reported that can automatically instrument arbitrary circuits on FPGAs with the measurement circuitry. On its own this measurement method is able to track the "health" of an integrated circuit, from commissioning through its lifetime, warning of impending failure or instigating pre-emptive degradation mitigation techniques. The use of the measurement method in a closed-loop dynamic voltage and frequency scaling scheme has been demonstrated, achieving significant improvements in power consumption and throughput performance.Open Acces

Techniques for Frequency Synthesizer-Based Transmitters.

Internet of Things (IoT) devices are poised to be the largest market for the semiconductor industry. At the heart of a wireless IoT module is the radio and integral to any radio is the transmitter. Transmitters with low power consumption and small area are crucial to the ubiquity of IoT devices. The fairly simple modulation schemes used in IoT systems makes frequency synthesizer-based (also known as PLL-based) transmitters an ideal candidate for these devices. Because of the reduced number of analog blocks and the simple architecture, PLL-based transmitters lend themselves nicely to the highly integrated, low voltage nanometer digital CMOS processes of today. This thesis outlines techniques that not only reduce the power consumption and area, but also significantly improve the performance of PLL-based transmitters.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/113385/1/mammad_1.pd