Co-design of a Class-D Oscillator and Dedicated DC-DC Power Converter

openL'obiettivo di questa tesi è stato lo sviluppo di un oscillatore in Classe-D direttamente alimentato da un convertitore DC/DC. Inoltre, è stata esplorata la possibilità di utilizzare il segnale di uscita fornito dall'oscillatore per fornire il segnale di switching al convertitore. I vari componenti del circuito sono stati analizzati concentrandosi sulle sfide progettuali di ciascun componente, sulla loro interazione reciproca e cercando, se possibile, di ottenere un circuito completamente integrato. Alcune possibili soluzioni vengono poi fornite alla fine della tesi, compresi i risultati delle simulazioni per i circuiti presentati.This thesis analyses the design problems behind the realization of an integrated oscillator directly powered by a switching voltage regulator. Additionally, the possibility of using the oscillator itself to provide the switching frequency for the converter is explored. The building blocks constituting the circuit are analysed focusing on the different design challenges of each component, on how they interact with each other and if it is possible to obtain a fully integrated design. Some possible design solutions are then provided at the end of the thesis including simulation results for the presented circuits

RF CMOS Transmitter Front-end with Output Power Combiner

In this thesis strategies to achieve a high efficiency RF front-end are studied and presented. A high efficiency Power Amplifier is also proposed and simulated. The applications for this type of designs are vast, but the main ones are in mobile transmission devices where the only power supply source available is a battery. In order to perform this thesis several topologies of power amplifiers were studied, and the decision fell to those based on a switching behavior. The reason for this decision was the need for high efficiency (it’s one of the main objectives). The Class-D power amplifier with its ideal potential efficiency of 100% has proven the most promising for implementation. The objectives for this thesis in terms of implementation were an efficiency of 20% and an output power of 0dBm. Finally, a power-combining technique was used to explore the potential of achieving high output power without affecting the efficiency

An enhanced swing differential Colpitts CMOS VCO for low-voltage operation

An enhanced swing differential Colpitts VCO (ESDC-VCO) dramatically improves the swing of a Colpitts VCO by allowing the signal to swing below ground and above the supply voltage. Fabricated in a 1P8M 0.13 um CMOS process, the ESDC-VCO operates at 4.9GHz with a 0.475-V supply and consumes 2.7mW. The measured phase noise is -136.2 dBc/Hz at a 3-MHz frequency offset. The ESDC-VCO employs digital amplitude control and achieves a Figure of merit (FOM) of 196.2 dBc/Hz, making it the highest performing integrated LC oscillator to date

High performance continuous-time filters for information transfer systems

Vast attention has been paid to active continuous-time filters over the years. Thus as the cheap, readily available integrated circuit OpAmps replaced their discrete circuit versions, it became feasible to consider active-RC filter circuits using large numbers of OpAmps. Similarly the development of integrated operational transconductance amplifier (OTA) led to new filter configurations. This gave rise to OTA-C filters, using only active devices and capacitors, making it more suitable for integration. The demands on filter circuits have become ever more stringent as the world of electronics and communications has advanced. In addition, the continuing increase in the operating frequencies of modern circuits and systems increases the need for active filters that can perform at these higher frequencies; an area where the LC active filter emerges. What mainly limits the performance of an analog circuit are the non-idealities of the used building blocks and the circuit architecture. This research concentrates on the design issues of high frequency continuous-time integrated filters. Several novel circuit building blocks are introduced. A novel pseudo-differential fully balanced fully symmetric CMOS OTA architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. On the level of system architectures, a novel filter low-voltage 4th order RF bandpass filter structure based on emulation of two magnetically coupled resonators is presented. A unique feature of the proposed architecture is using electric coupling to emulate the effect of the coupled-inductors, thus providing bandwidth tuning with small passband ripple. As part of a direct conversion dual-mode 802.11b/Bluetooth receiver, a BiCMOS 5th order low-pass channel selection filter is designed. The filter operated from a single 2.5V supply and achieves a 76dB of out-of-band SFDR. A digital automatic tuning system is also implemented to account for process and temperature variations. As part of a Bluetooth transmitter, a low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications

An Energy-Efficient Reconfigurable Mobile Memory Interface for Computing Systems

The critical need for higher power efficiency and bandwidth transceiver design has significantly increased as mobile devices, such as smart phones, laptops, tablets, and ultra-portable personal digital assistants continue to be constructed using heterogeneous intellectual properties such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors, dynamic random-access memories (DRAMs), sensors, and graphics/image processing units and to have enhanced graphic computing and video processing capabilities. However, the current mobile interface technologies which support CPU to memory communication (e.g. baseband-only signaling) have critical limitations, particularly super-linear energy consumption, limited bandwidth, and non-reconfigurable data access. As a consequence, there is a critical need to improve both energy efficiency and bandwidth for future mobile devices.;The primary goal of this study is to design an energy-efficient reconfigurable mobile memory interface for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed energy efficient mobile memory interface which utilizes an advanced base-band (BB) signaling and a RF-band signaling is capable of simultaneous bi-directional communication and reconfigurable data access. It also increases power efficiency and bandwidth between mobile CPUs and memory subsystems on a single-ended shared transmission line. Moreover, due to multiple data communication on a single-ended shared transmission line, the number of transmission lines between mobile CPU and memories is considerably reduced, resulting in significant technological innovations, (e.g. more compact devices and low cost packaging to mobile communication interface) and establishing the principles and feasibility of technologies for future mobile system applications. The operation and performance of the proposed transceiver are analyzed and its circuit implementation is discussed in details. A chip prototype of the transceiver was implemented in a 65nm CMOS process technology. In the measurement, the transceiver exhibits higher aggregate data throughput and better energy efficiency compared to prior works

Low Power Adaptive Circuits: An Adaptive Log Domain Filter and A Low Power Temperature Insensitive Oscillator Applied in Smart Dust Radio

This dissertation focuses on exploring two low power adaptive circuits. One is an adaptive filter at audio frequency for system identification. The other is a temperature insensitive oscillator for low power radio frequency communication. The adaptive filter is presented with integrated learning rules for model reference estimation. The system is a first order low pass filter with two parameters: gain and cut-off frequency. It is implemented using multiple input floating gate transistors to realize online learning of system parameters. Adaptive dynamical system theory is used to derive robust control laws in a system identification task. Simulation results show that convergence is slower using simplified control laws but still occurs within milliseconds. Experimental results confirm that the estimated gain and cut-off frequency track the corresponding parameters of the reference filter. During operation, deterministic errors are introduced by mismatch within the analog circuit implementation. An analysis is presented which attributes the errors to current mirror mismatch. The harmonic distortion of the filter operating in different inversion is analyzed using EKV model numerically. The temperature insensitive oscillator is designed for a low power wireless network. The system is based on a current starved ring oscillator implemented using CMOS transistors instead of LC tank for less chip area and power consumption. The frequency variance with temperature is compensated by the temperature adaptive circuits. Experimental results show that the frequency stability from 5°C to 65°C has been improved 10 times with automatic compensation and at least 1 order less power is consumed than published competitors. This oscillator is applied in a 2.2GHz OOK transmitter and a 2.2GHz phase locked loop based FM receiver. With the increasing needs of compact antenna, possible high data rate and wide unused frequency range of short distance communication, a higher frequency phase locked loop used for BFSK receiver is explored using an LC oscillator for its capability at 20GHz. The success of frequency demodulation is demonstrated in the simulation results that the PLL can lock in 0.5μs with 35MHz lock-in range and 2MHz detection resolution. The model of a phase locked loop used for BFSK receiver is analyzed using Matlab

On the design of ultra low voltage CMOS oscillators.

Wireless sensor nodes require very tight power budgets to operate from either asmall battery, some energy harvesting mechanism or both. In many cases, thermalor electrochemical harvesting devices provide very low voltages of the order of100 mV or even lower. Time-keeping functionality is required in IoT systems andthe time-keeping module must be on at all times. Crystal oscillators have provento be useful for low power time-keeping applications, and in this context supplyvoltage lowering is a convenient strategy. Therefore, 32 kHz crystal oscillatorsoperating with only 60 mV supply are presented. Two implementations based ona Schmitt trigger circuit for two different crystals were designed and experimentallycharacterized.These crystal oscillators are based on the application of a Schmitt trigger asan amplifier. Guidelines for designing this block to be the amplifier of a crystaloscillator are provided. Furthermore, a dynamic model of the Schmitt trigger isproposed and the model results are compared against simulations. The amplifierswere experimentally characterized, providing a gain of 2.48 V/V with a 60 mVpower supply. As it was intended in the design stage, for voltages above 100 mVhysteresis appears and the Schmitt trigger starts operating as a comparator.The Schmitt triggers to operate as amplifiers of the crystal oscillators aredesigned in a 130 nm CMOS process, requiring an area of 45μm x 74μm and78μm x 83μm, respectively. The power consumptions of the crystal oscillators are2.26 nW and 15 nW and the temperature stabilities attained are 62 ppm (25-62°C)and 50 ppm (5-62°C), respectively. The dependence on the supply voltage of thecurrent consumption, fractional frequency, start-up time and oscillation amplitudewere measured. The Allan deviation is 30 ppb for both oscillators.On the other hand, an LC voltage controlled oscillator (VCO) is designed in28 nm FD-SOI for RF applications. The possibility of modeling the transistors inthe 28 nm FD-SOI technology by means of the all inversion region long channelbulk transistor model used for the Schmitt trigger circuits, is studied. A cross-coupled nMOS architecture is used to build the VCO. The theoretical limit for theminimum supply voltage that enables oscillation is studied. The transistors wereoptimally sized to aim the minimum power consumption through a low-voltageapproach and the performance of the VCO was obtained through simulations. Los nodos sensores inalámbricos tienen fuertes requerimientos de bajo consumo demanera de operar con baterías pequeñas o algún mecanismo de cosecha de energía, o ambos. En muchos casos, la cosecha de energía térmica o electroquímica provee tensiones muy bajas del orden de 100 mV o incluso menos. Los sistemas de internet de las cosas incluyen un módulo de reloj que debe estar siempre encendido a efectos de contar el tiempo. Los osciladores a cristal son probadamente ́utiles como relojes de bajo consumo, y en este contexto la reducción de la tensión es una estrategia conveniente. Por lo tanto, presentamos osciladores a cristal de 32 kHz operando con sólo 60 mV de tensión de alimentación. Dos implementaciones, basadas en el circuito Schmitt trigger para dos cristales diferentes, se diseñan y caracterizan experimentalmente.Estos osciladores a cristal están basados en la aplicación del Schmitt trigger como amplificador. Se provee una guía para el diseño de este bloque para funcionar como el amplificador de un oscilador a cristal. Adicionalmente se propone un modelo dinámico del Schmitt trigger y los resultados del modelo son comparados con resultados de simulación. Los amplificadores son caracterizados experimentalmente, proveyendo una ganancia de 2.48 V/V con 60 mV de tensión de alimentación. Tal como se pretende en la etapa de diseño, para tensiones mayores a 100 mV aparece el fenómeno de histéresis y el Schmitt trigger comienza a operarcomo un comparador.Los Schmitt trigger para operar como amplificadores de los osciladores a cristal son diseñados en un proceso CMOS de 130 nm y ocupan un área de 45μm x 74μmy 78μm x 83μm, respectivamente. El consumo de potencia de sendos osciladores es2.26 nW y 15 nW y la estabilidad en temperatura obtenida es de 62 ppm (25-62°C)y 50 ppm (5-62°C), respectivamente. Se midieron la dependencia del consumo de corriente con respecto a la tensión de alimentación, la frequencia de oscilación, eltiempo de arranque y la amplitud de oscilación. La desviación de Allan es 30 ppben ambos osciladores.Por otra parte, un oscilador LC controlado por voltaje es diseñado en un proceso CMOS de silicio sobre aislante en deplexión total de 28 nm, para aplicaciones de radiofrecuencia. Se estudia la posibilidad de utilizar en este caso el mismo modelo utilizado para el diseño del Schmitt trigger. Dicho modelo es válido en todas las regiones de inversión y está desarrollado para transistores de tipo sustrato y de canal largo. La arquitectura de transistores nMOS entrelazados es la utilizada para este oscilador. Se estudia el límite teórico para la mínima tensión de alimentación. Los transistores son dimensionados de manera óptima para obtener el mínimo consumo de potencia posible, utilizando un enfoque de baja tensión y el desempeño del oscilador se obtuvo mediante simulaciones

45-nm SOI CMOS Bluetooth Electrochemical Sensor for Continuous Glucose Monitoring

Due to increasing rates of diabetes, non-invasive glucose monitoring systems will become critical to improving health outcomes for an increasing patient population. Bluetooth integration for such a system has been previously unattainable due to the prohibitive energy consumption. However, enabling Bluetooth allows for widespread adoption due to the ubiquity of Bluetooth-enabled mobile devices. The objective of this thesis is to demonstrate the feasibility of a Bluetooth-based energy-harvesting glucose sensor for contact-lens integration using 45~nm silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology. The proposed glucose monitoring system includes a Bluetooth transmitter implemented as a two-point closed loop PLL modulator, a sensor potentiostat, and a 1st-order incremental delta-sigma analog-to-digital converter (IADC). This work details the complete system design including derivation of top-level specifications such as glucose sensing range, Bluetooth protocol timing, energy consumption, and circuit specifications such as carrier frequency range, output power, phase-noise performance, stability, resolution, signal-to-noise ratio, and power consumption. Three test chips were designed to prototype the system, and two of these were experimentally verified. Chip 1 includes a partial implementation of a phase-locked-loop (PLL) which includes a voltage-controlled-oscillator (VCO), frequency divider, and phase-frequency detector (PFD). Chip 2 includes the design of the sensor potentiostat and IADC. Finally, Chip 3 combines the circuitry of Chip 1 and Chip 2, along with a charge-pump, loop-filter and power amplifier to complete the system. Chip 1 DC power consumption was measured to be 204.8~$\mu$W, while oscillating at 2.441 GHz with an output power $P_{out}$ of -35.8 dBm, phase noise at 1 MHz offset $L(1\text{ MHz})$ of -108.5 dBc/Hz, and an oscillator figure of merit (FOM) of 183.44dB. Chip 2 achieves a total DC power consumption of 5.75~$\mu$W. The system has a dynamic range of 0.15~nA -- 100~nA at 10-bit resolution. The integral non-linearity (INL) and differential non-linearity (DNL) of the IADC were measured to be -6~LSB/$\pm$0.3~LSB respectively with a conversion time of 65.56~ms. This work achieves the best duty-cycled DC power consumption compared to similar glucose monitoring systems, while providing sufficient performance and range using Bluetooth

On the design of ultra low voltage CMOS oscillators

Los nodos sensores inalámbricos tienen fuertes requerimientos de bajo consumo de manera de operar con baterías pequeñas o algún mecanismo de cosecha de energía, o ambos. En muchos casos, la cosecha de energía térmica o electroquímica provee tensiones muy bajas del orden de 100 mV o incluso menos. Los sistemas de internet de las cosas incluyen un módulo de reloj que debe estar siempre encendido a efectos de contar el tiempo. Los osciladores a cristal son probadamente útiles como relojes de bajo consumo, y en este contexto la reducción de la tensión es una estrategia conveniente. Por lo tanto, presentamos osciladores a cristal de 32 kHz operando con sólo 60 mV de tensión de alimentación. Dos implementaciones, basadas en el circuito Schmitt trigger para dos cristales diferentes, se diseñan y caracterizan experimentalmente. Estos osciladores a cristal están basados en la aplicación del Schmitt trigger como amplificador. Se provee una guía para el diseño de este bloque para funcionar como el amplificador de un oscilador a cristal. Adicionalmente se propone un modelo dinámico del Schmitt trigger y los resultados del modelo son comparados con resultados de simulación. Los amplificadores son caracterizados experimentalmente, proveyendo una ganancia de 2.48 V/V con 60 mV de tensión de alimentación. Tal como se pretende en la etapa de diseño, para tensiones mayores a 100 mV aparece el fenómeno de histéresis y el Schmitt trigger comienza a operar como un comparador. Los Schmitt trigger para operar como amplificadores de los osciladores a cristal son diseñados en un proceso CMOS de 130 nm y ocupan un área de 45 um x 74 um y 78 um x 83 um, respectivamente. El consumo de potencia de sendos osciladores es 2.26 nW y 15 nW y la estabilidad en temperatura obtenida es de 62 ppm (25-62°C) y 50 ppm (5-62°C), respectivamente. Se midieron la dependencia del consumo de corriente con respecto a la tensión de alimentación, la frequencia de oscilación, el tiempo de arranque y la amplitud de oscilación. La desviación de Allan es 30 ppb en ambos osciladores. Por otra parte, un oscilador LC controlado por voltaje es diseñado en un proceso CMOS de silicio sobre aislante en deplexión total de 28 nm, para aplicaciones de radiofrecuencia. Se estudia la posibilidad de utilizar en este caso el mismo modelo utilizado para el diseño del Schmitt trigger. Dicho modelo es válido en todas las regiones de inversión y está desarrollado para transistores de tipo sustrato y de canal largo. La arquitectura de transistores nMOS entrelazados es la utilizada para este oscilador. Se estudia el límite teórico para la mínima tensión de alimentación. Los transistores son dimensionados de manera óptima para obtener el mínimo consumo de potencia posible, utilizando un enfoque de baja tensión y el desempeño del oscilador se obtuvo mediante simulaciones.Agencia Nacional de Investigación e InnovaciónComisión Académica de Posgrado. Universidad de la RepúblicaComisión Sectorial de Investigación Científica. Universidad de la Repúblic

Giga-hertz CMOS voltage controlled oscillators.

Leung Lai-Kan.Thesis (M.Phil.)--Chinese University of Hong Kong, 2001.Includes bibliographical references (leaves 131-154).Abstracts in English and Chinese.Abstract --- p.iAcknowledgement --- p.iiiTable of Contents --- p.ivList of Figures --- p.ixList of Tables --- p.xvChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Overview --- p.1Chapter 1.2 --- Objectives --- p.2Chapter 1.3 --- Thesis Organization --- p.4Chapter Chapter 2 --- Fundamentals of Voltage Controlled Oscillators --- p.6Chapter 2.1 --- Definition of Commonly Used Figures of Merit --- p.6Chapter 2.1.1 --- Cutoff frequency --- p.6Chapter 2.1.2 --- Center Frequency --- p.8Chapter 2.1.3 --- Tuning Range --- p.8Chapter 2.1.4 --- Tuning Sensitivity --- p.8Chapter 2.1.5 --- Output Power --- p.8Chapter 2.1.6 --- Power Consumption --- p.9Chapter 2.1.7 --- Supply Pulling --- p.9Chapter 2.2 --- Phase Noise --- p.9Chapter 2.2.1 --- Definition of Phase Noise --- p.9Chapter 2.2.2 --- Phase Noise Specification --- p.11Chapter 2.2.3 --- Leeson's formula --- p.12Chapter 2.2.4 --- Models developed by J. Cranincks and M. Steyaert10 --- p.13Chapter 2.2.5 --- Linear Time-Variant Phase Noise Model --- p.13Chapter 2.3 --- Building Blocks of Voltage Controlled Oscillators --- p.17Chapter 2.3.1 --- FETs --- p.17Chapter 2.3.2 --- Varactor --- p.18Chapter 2.3.3 --- Spiral Inductor --- p.21Chapter 2.3.4 --- Modeling of the Spiral Inductor --- p.24Chapter 2.3.5 --- Analysis and Simulation --- p.26Chapter Chapter 3 --- Digital Controlled Oscillator --- p.28Chapter 3.1 --- Introduction --- p.28Chapter 3.2 --- General Principle of Oscillation --- p.28Chapter 3.3 --- Different Oscillator Architectures --- p.30Chapter 3.3.1 --- Single-ended Ring Oscillator --- p.30Chapter 3.3.2 --- Differential Ring Oscillator --- p.32Chapter 3.3.3 --- CMOS Injection-locked Oscillator --- p.33Chapter 3.4 --- Basic Principle of the Injection-locked Oscillator --- p.34Chapter 3.5 --- Digital Controlled Oscillator --- p.36Chapter 3.5.1 --- R-2R Digital-to-Analog Converter --- p.37Chapter 3.6 --- Injection Locking --- p.42Chapter 3.6.1 --- Synchronization Model of the Injection Locked Oscillator --- p.42Chapter 3.7 --- Simulation Results --- p.44Chapter 3.7.1 --- Frequency Tuning Characteristics --- p.44Chapter 3.7.2 --- Phase Noise Performance --- p.47Chapter 3.7.3 --- Locking Characteristics --- p.48Chapter 3.7.4 --- Sensitivity to Supply Voltage and Temperature --- p.48Chapter 3.8 --- Conclusion --- p.49Chapter Chapter 4 --- CMOS LC Voltage Controlled Oscillator --- p.51Chapter 4.1 --- Introduction --- p.51Chapter 4.2 --- LC Oscillator --- p.52Chapter 4.3 --- Circuit Design --- p.54Chapter 4.3.1 --- Oscillation Frequency --- p.55Chapter 4.3.2 --- Oscillation Amplitude --- p.58Chapter 4.3.3 --- Transistor Sizing --- p.59Chapter 4.3.4 --- Power Consumption --- p.62Chapter 4.3.5 --- Tuning Range --- p.62Chapter 4.3.6 --- Phase Noise Analysis --- p.63Chapter 4.4 --- Conclusion --- p.70Chapter Chapter 5 --- LC Quadrature Voltage Controlled Oscillator --- p.71Chapter 5.1 --- Introduction --- p.71Chapter 5.2 --- Conventional CMOS Quadrature LC Voltage Controlled Oscillator --- p.73Chapter 5.3 --- Operational Principle of the CMOS Quadrature LC Voltage Controlled Oscillator --- p.74Chapter 5.3.1 --- General Explanation --- p.74Chapter 5.3.2 --- Mathematical Analysis --- p.75Chapter 5.3.3 --- Drawback of the Conventional CMOS LC Quadrature VCO --- p.77Chapter 5.4 --- Novel CMOS Low Noise Quadrature Voltage Controlled Oscillator --- p.78Chapter 5.4.1 --- Equivalent Output Noise due to the Coupling Transistor --- p.80Chapter 5.4.2 --- Linear Time Varying Model for the Analysis of Total Phase Noise --- p.83Chapter 5.4.3 --- Tuning Range --- p.94Chapter 5.4.4 --- Start-up Condition --- p.95Chapter 5.4.5 --- Power Consumption --- p.97Chapter 5.5 --- New Tuning Mechanism of the Proposed LC Quadrature VCO --- p.98Chapter 5.6 --- Modified Version of the Proposed LC Quadrature Voltage Controlled Oscillator --- p.105Chapter 5.7 --- Conclusion --- p.108Chapter Chapter 6 --- Layout Consideration --- p.109Chapter 6.1 --- Substrate Contacts --- p.109Chapter 6.2 --- Guard Rings --- p.110Chapter 6.3 --- Thermal Noise of the Gate Interconnect --- p.111Chapter 6.4 --- Use of Different Layers of Metal for Interconnection --- p.112Chapter 6.5 --- Slicing of Transistors --- p.113Chapter 6.6 --- Width of Interconnecting Wires and Numbers of Vias --- p.114Chapter 6.7 --- Matching of Devices --- p.114Chapter 6.8 --- Die Micrographs of the Prototypes of the Oscillators --- p.115Chapter Chapter 7 --- Experimental Results --- p.118Chapter 7.1 --- Methodology --- p.118Chapter 7.2 --- Evaluation Board --- p.119Chapter 7.3 --- Measurement Setup --- p.123Chapter 7.4 --- Experimental Results --- p.125Chapter 7.4.1 --- CMOS Injection Locked Oscillator --- p.125Chapter 7.4.2 --- LC Differential Voltage Controlled Oscillator --- p.128Chapter 7.4.3 --- LC Quadrature Voltage Controlled Oscillator --- p.132Chapter 7.5 --- Summary of Performance --- p.139Chapter Chapter 8 --- Conclusion --- p.142Chapter 8.1 --- Contribution --- p.142Chapter 8.2 --- Further Development --- p.143Chapter Chapter 9 --- Appendix --- p.145Chapter 9.1 --- Circuit Transformation --- p.145Chapter 9.2 --- Derivation of the Inductor Model with PGS --- p.146Chapter 9.2.1 --- "Inductance," --- p.146Chapter 9.2.2 --- "Series Resistance, Rs" --- p.146Chapter 9.2.3 --- Series Capacitance --- p.147Chapter 9.2.4 --- Shunt Oxide Capacitance --- p.147Chapter 9.3 --- Calculation of Phase Noise Using the Linear Time Variant Model --- p.148Chapter Chapter 10 --- Bibliography --- p.15