Hierarchical Agent-based Adaptation for Self-Aware Embedded Computing Systems

Siirretty Doriast

Thermal Management for Dependable On-Chip Systems

This thesis addresses the dependability issues in on-chip systems from a thermal perspective. This includes an explanation and analysis of models to show the relationship between dependability and tempature. Additionally, multiple novel methods for on-chip thermal management are introduced aiming to optimize thermal properties. Analysis of the methods is done through simulation and through infrared thermal camera measurements

New Design Techniques for Dynamic Reconfigurable Architectures

L'abstract è presente nell'allegato / the abstract is in the attachmen

Developing a distributed electronic health-record store for India

The DIGHT project is addressing the problem of building a scalable and highly available information store for the Electronic Health Records (EHRs) of the over one billion citizens of India

Network-on-Chip -based Multi-Processor System-on-Chip: Towards Mixed-Criticality System Certification

L'abstract è presente nell'allegato / the abstract is in the attachmen

Towards an Energy-Aware Framework for Application Development and Execution in Heterogeneous Parallel Architectures

The Transparent heterogeneous hardware Architecture deployment for eNergy Gain in Operation (TANGO) project’s goal is to characterise factors which affect power consumption in software development and operation for Heterogeneous Parallel Hardware (HPA) environments. Its main contribution is the combination of requirements engineering and design modelling for self-adaptive software systems, with power consumption awareness in relation to these environments. The energy efficiency and application quality factors are integrated into the application lifecycle (design, implementation and operation). To support this, the key novelty of the project is a reference architecture and its implementation. Moreover, a programming model with built-in support for various hardware architectures including heterogeneous clusters, heterogeneous chips and programmable logic devices is provided. This leads to a new cross-layer programming approach for heterogeneous parallel hardware architectures featuring software and hardware modelling. Application power consumption and performance, data location and time-criticality optimization, as well as security and dependability requirements on the target hardware architecture are supported by the architecture

The Space Technology 8 Mission

The Space Technology 8 (ST8) mission is the latest in NASA’s New Millennium Program technology demonstration missions. ST8 includes a spacecraft bus built by industry, flying four new technology payloads in low- Earth orbit. This paper will describe each payload, along with a brief description of the mission and spacecraft. The payloads include a miniature loop heat pipe intended to save mass and power on future small satellites, designed and built by NASA’s Goddard Space Flight Center; a lightweight, 35g/m linear mass, 40-m deployable boom intended as a future solar sail mast built by ATK Space Systems; a deployable, lightweight Ultraflex solar array producing 175W/kg, also built by ATK Space Systems; and a high-speed, parallel-processing computer system built of state-of-the-art COTS processors, demonstrating SEU tolerance without the need for radiation-hardened electronics, and 100M operations per second per Watt processing throughput density