Dual Slope ADC Design from Power, Speed and Area Perspectives

© ASEE 2009The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. In this paper, the design optimization of a 8-bit dual-slope ADC from power, speed and area perspectives is proposed. The proposed ADC consists of an analog part (including an integrator and a comparator) and a digital part (including a controller, counter and 8-bit register). Both D and T flip-flops are utilized in the ADC design to demonstrate its influence on area, performance (speed) and power by using different types of flip-flops. The layout of the ADC is designed with Mentor Graphics IC Station. The netlisted is extracted from the layout to include the parasitic capacitances for a more accurate power analysis. PSPICE power simulation is performed to read the power consumption of the ADC for the given inputs. Some efforts on reducing the power consumption of the ADC are also made. For example, the clock signal feeding to the flip-flops is revised to be data dependent so that the clock may be disabled to avoid unnecessary switches whenever it is possible. In this way, the overall power consumption of the ADC is reduced. Double-edge triggered (DET) flip-flops are also used in register circuitry. Since the DET flip-flops trigger at both the rising and falling edges, the clock signal is utilized to the fullest. The proposed dualslope ADC can be used for applications requiring an optimum chip area, minimum power consumption and excellent performance

Analog/digital pH meter system I.C.

The project utilizes design automation software tools to design, simulate, and fabricate a pH meter integrated circuit (IC) system including a successive approximation type seven-bit analog to digital converter circuits using a 1.25 micron N-Well CMOS MOSIS process. The input voltage ranges from 0.5 to 1.0 V derived from a special type pH sensor, and the output is a three-digit decimal number display of pH with one decimal point

The 1992 4th NASA SERC Symposium on VLSI Design

Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design

VIPER : a 25-MHz, 100-MIPS peak VLIW micro-processor

This paper describes the design and implementation of a very long instruction word (VLIW) microprocessor. The VIPER (VLIW integer processor) contains four pipelined functional units, and can achieve 100 MIPS peak performance at 25 MHz. The procesor is capable of performing multiway branch operations, two load/store operations and up to four ALU operations in each clock cycle, with full register file access to each functional unit. VIPER is the first VLIW microprocessor known that can achieve this level of performance. Designed in twelve months, the processor is integrated with an instruction cache controller and a data cache, requiring 450,000 transistors and a die size of 12.9 by 9.1 mm in a 1.2 µm technology

A Morphological array image processor controller chip set

The design, simulation and layout of a controller chip set for a morphological array image processor shall be discussed. These VLSI chips in conjunction with the Morphological Array Processor (MAP) and Arithmetic Logic Unit (ALU) chip sets perform the morphological image processing operations of erosion and dilation on 512x512 pixel, 8-bit gray scale images using a 7x7 windowing matrix in real time (60 frames per second). The controller chip set design allows for pipelining of successive MAP\u27s as well as operation on 1024x1024 pixel, 8-bit gray scale images. To facilitate the design, additional scaleable CMOS standard library cells and corresponding parameterized schematic library components were designed and integrated with the RIT CMOS standard cell library designed by Computer Engineering graduate student Larry Rubin as part of his Masters thesis1. In particular, additional D flip-flops with both Q and Q bar outputs, and-orinverts, or-and-inverts, CMUXes, and MOSIS 64 and 84 pin pad rings were created. The cells were designed to be fabricated using the Metal Oxide Semiconductor Implementation System (MOSIS) scaleable CMOS 2.0 pm Nwell (SCN) process. A complete set of Cadence design rule verification tools were also integrated with the existing CAE tool set to perform design rule checking (DRC), electrical rule checking (ERC), layout versus schematic checking (LVS), and layout parameter extraction (LPE) for the MOSIS SCN 2.0 pm N-well dense rule set. To verify the CMOS standard cell designs, test chips were designed and sent to MOSIS for fabrication. The layout and design rule verification of the final two test chips, test chips five and six, was performed by the author. Test chip four contains a variety of MUXes and D flip-flops, test chip five contains a variety of transfer gates and inverters. The controller chip set consists of a 64 pin control chip (Controller) and an 84 pin memory controller chip (Mem_Control). The controller chips provide the ability to selectively process 512x512 or 1024x1024 image sizes by modifying the pullup or pulldown of a size bit. A selectable delay was implemented, through the pullup or pulldown setup of three delay bits, in the Controller to allow the Controller to be used with the single chip VLSI MAP design, the seven chip VLSI MAP design, and the Actel gate array MAP. The controller chip set allows successive MAPs to be pipelined by connecting the next Controllers pipeline start pin to the previous stages pipeline start next pin

High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip

With higher-level integration driven by increasingly complex digital systems and downscaling CMOS processes available, system-on-a-chip (SoC) is an emerging technology of low power, high cost effectiveness and high reliability and is exceedingly attractive for applications in high-speed data conversion wireless and wideband communication systems. This research presents a novel ADC comparator design methodology; the speed and performance of which is not restricted by the supply voltage reduction and device linearity deterioration in scaling-down CMOS processes. By developing a dynamic offset suppression technique and a circuit optimization method, the comparator can achieve a 3 dB frequency of 2 GHz in 130 nanometer (nm) CMOS process. Combining this new comparator design and a proposed pipelined thermometer-Gray- binary encoder designed by the DCVSPG logic, a high-speed, low-voltage clocked-digital- comparator (CDC) pipelined CMOS flash ADC architecture is proposed for wideband communication SoC. This architecture has advantages of small silicon area, low power, and low cost. Three CDC-based pipelined CMOS flash ADCs were implemented in 130 nm CMOS process and their experimental results are reported: 1. 4-b, 2.5-GSPS ADC: SFDR of 21.48-dB, SNDR of 15.99-dB, ENOB of 2.4-b, ERBW of 1-GHz, power of 7.9-mW, and area of 0.022-mm2. 2. 4-b, 4-GSPS ADC: SFDR of 25-dB, SNDR of 18.6-dB, ENOB of 2.8-b, ERBW of 2-GHz, power of 11-mW. 3. 6-b, 4-GSPS ADC: SFDR of 48-dB at a signal frequency of 11.72-MHz, SNDR of 34.43-dB, ENOB of 5.4-b, power of 28-mW. An application of the proposed CDC-based pipelined CMOS flash ADC is 1-GHz bandwidth, 2.5-GSPS digital receiver on a chip. To verify the performance of the receiver, a mixed-signal block-level simulation and verification flow was built in Cadence AMS integrated platform. The verification results of the digital receiver using a 4-b 2.5-GSPS CDC-based pipelined CMOS ADC, a 256-point, 12-point kernel function FFT and a frequency detection logic show that two tone signals up to 1125 MHz can be detected and discriminated. A notable contribution of this research is that the proposed ADC architecture and the comparator design with dynamic offset suppression and optimization are extremely suitable for future VDSM CMOS processes and make all-digital receiver SoC design practical

Concurrent focal-plane generation of compressed samples fromtime-encoded pixel values

Compressive sampling allows wrapping the relevant content of an image in a reduced set of data. It exploits the sparsity of natural images. This principle can be employed to deliver images over a network under a restricted data rate and still receive enough meaningful information. An efficient implementation of this principle lies in the generation of the compressed samples right at the imager. Otherwise, i. e. digitizing the complete image and then composing the compressed samples in the digital plane, the required memory and processing resources can seriously compromise the budget of an autonomous camera node. In this paper we present the design of a pixel architecture that encodes light intensity into time, followed by a global strategy to pseudo-randomly combine pixel values and generate, on-chip and on-line, the compressed samples.Ministerio de Economía y Competitividad TEC 2015-66878-C3-1-RJunta de Andalucía TIC 2338-2013Office of Naval Research (USA) N000141410355CONACYT (Mexico) MZO-2017-29106

Implementation of a 200 MSps 12-bit SAR ADC

Analog-to-digital converters (ADCs) with high conversion frequency, often based on pipelined architectures, are used for measuring instruments, wireless communication and video applications. Successive approximation register (SAR) converters offer a compact and power efficient alternative but the conversion speed is typically designed for lower frequencies. In this thesis a low-power 12-bit 200 MSps SAR ADC based on charge redistribution was designed for a 28 nm CMOS technology. The proposed design uses an efficient SAR algorithm (merged capacitor switching procedure) to reduce power consumption due to capacitor charging by 88 % compared to a conventional design, as well as reducing the total capacitor area by half. Sampling switches were bootstrapped for increased linearity compared to simple transmission gates. Another feature of the low power design is a fully-dynamic comparator which does not require a preamplifier. Pre-layout simulations of the SAR ADC with 800 MHz input frequency shows an SNDR of 64.8 dB, corresponding to an ENOB of 10.5, and an SFDR of 75.3 dB. The total power consumption is 1.77 mW with an estimated value of 500 W for the unimplemented digital logic. Calculation of the Schreier figure-of-merit was done with an input signal at the Nyquist frequency. The simulated SNDR, SFDR and power equals 69.5 dB, 77.3 dB and 1.9 mW respectively, corresponding to a figure-of merit of 176.6 dB.Från analogt till digitalt - snabba och strömsnåla omvandlare Dagens digitala samhälle ställer höga krav på prestanda och effektivitet. I samarbete med Ericsson i Lund har en krets för signalomvandling utvecklats. Genom smart design uppnås hög hastighet och låg strömförbrukning som ligger i forskningens framkant. Från analogt till digitalt Ett viktigt byggblock för telekommunikation och videoapplikationer är så kallade A/D-omvandlare, som översätter mellan analoga signaler (till exempel ljud) och digitala signaler bestående av ettor och nollor. En väldigt effektiv metod för A/D-omvandling bygger på så kallad successiv approximation. Metoden innebär att signalen som ska omvandlas jämförs med en referensnivå, som stegvis justeras för att närma sig signalens värde. Till slut har man en tillräckligt god uppskattning av värdet som ska mätas. Just en sådan omvandlare har utvecklats med höga krav på hastighet och energiförbrukning. Detta gjordes genom datorsimuleringar av modeller som beskriver kretsen. Referensnivån skapas ofta genom att styra ett nätverk som lagrar elektrisk laddning. Omvandlingens noggrannhet, eller upplösning, beror på hur många nivåer som finns tillgängliga det vill säga hur nära signalens värde man kan komma. I den designade kretsen finns hela 4096 nivåer! Det finns många källor till osäkerhet i systemet, bland annat hur exakta referensnivåerna är och hur bra jämförelsen med insignalen kan göras. Eftersom dessa eventuellt kan leda till en försämring av omvandlingens noggrannhet måste alla delar i kretsen utformas med detta i åtanke. Höga hastigheter Eftersom det krävs många steg för referensnivån att närma sig signalens värde är den maximala omvandlingshastigheten ofta begränsad. Med teknikens utveckling öppnas nya möjligheter i takt med att mikrochippens enskilda komponenter blir snabbare. Modern forskning visar att omvandlare baserade på successiv approximation kan uppnå hastigheter på flera miljoner mätvärden varje sekund, vilket även den utvecklade kretsen klarar av. Effektiv design Nya metoder för successiv approximation möjliggör stora besparingar när det gäller effektförbrukning, till exempel genom att effektivisera upp- och urladdningen av nätverket. Genom små ändringar kunde nätverkets energiförbrukning minskas med över 90 % samtidigt som dess area halverades. Eftersom produktionskostnaden för integrerade kretsar är hög medför varje minskning av kretsens area att kostnaden sjunker