HIGH THROUGHPUT IMPLEMENTATION OF 64 BIT MODIFIED WALLANCE MAC USING MULTIOPERAND ADDERS

Although redundant addition is widely used to design parallel multioperand adders for ASIC implementations, the use of redundant adders on Field Programmable Gate Arrays (FPGAs) has generally been avoided. The main reasons are the efficient implementation of carry propagate adders (CPAs) on these devices (due to their specialized carry-chain resources) as well as the area overhead of the redundant adders when they are implemented on FPGAs. This project presents different approaches to the efficient implementation of generic carry-save compressor trees. In computing, especially digital signal processing, the multiply–accumulate operation is a common step that computes the product of two numbers and adds that product to an accumulator. The hardware unit that performs the operation is known as a multiplier–accumulator (MAC, or MAC unit); the operation itself is also often called a MAC or a MAC operation. Power dissipation is one of the most important design objectives in integrated circuit, after speed. Digital signal processing (DSP) circuits whose main building block is a Multiplier-Accumulator (MAC) unit. High speed and low power MAC unit is desirable for any DSP processor. This is because speed and throughput rate are always the concerns of DSP system. MAC unit consists of adder, multiplier, and an accumulator it preserves a unique mapping between input and output vector of the particular circuit. In this MAC operation is performed in two parts Partial Product Generation (PPG) circuit and Multi-Operand Addition (MOA) circui

Multichannel arbitrary waveform beamformer transmitter for experimental research activities of ultrasound

This paper presents the development of a digital beamformer transmitter system for generation of arbitrary ultrasound waveforms, specifically designed for research purposes. The proposed architecture has 8 independent excitation channels and uses an FPGA device (Field Programmable Gated Array) for electronic control channel generation of ultrasonic acoustic beam transmission. The system allows operation in pulse-echo mode, with pulse repetition rate of excitation between 62.5 Hz and 8 kHz, or single pulse, center frequency between 500 kHz and 20 MHz, excitation voltage between -100 and +100 V, and individual control of amplitude apodization, phase angle and time delay trigger. The mathematical method for determining the digital signals of excitation is presented and validated through practical results for waveform generation with Gaussian profile and center frequency of 20 MHz, in a load formed by a 220 pF capacitor in parallel with a resistor of 1 k Ω. The results show that the proposed flexible and fully programmable architecture, can support the development of new algorithms and sophisticated processing techniques of the transmission beamformer.Este trabalho apresenta o desenvolvimento de um sistema digital beamformer de transmissão para geração de formas de onda arbitrárias de ultrassom, projetado especificamente para fins de pesquisa. A arquitetura proposta possui 8 canais de excitação independentes e utiliza um dispositivo FPGA (Field Programmable Gated Array) para controle eletrônico dos canais de geração do feixe acústico ultrassônico de transmissão. O sistema permite operação no modo pulso-eco, com taxa de repetição dos pulsos de excitação entre 62,5 Hz e 8 kHz, ou pulso único, frequência central entre 500 kHz e 20 MHz, tensão de excitação entre -100 V e +100 V, e controle individual da amplitude de apodização, ângulo de fase e atraso temporal de disparo. O método matemático para determinação dos sinais digitais de excitação é apresentado e validado através dos resultados práticos para geração de forma de onda com perfil Gaussiano e frequência central de 20 MHz, em uma carga equivalente formada por um capacitor de 220 pF em paralelo com um resistor de 1 k Ω. Os resultados demonstram que a arquitetura flexível e totalmente programável proposta, pode apoiar o desenvolvimento de novos algoritmos e técnicas sofisticadas de processamento do beamformer de transmissão.667678Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq

Computer-Assisted Algorithms for Ultrasound Imaging Systems

Ultrasound imaging works on the principle of transmitting ultrasound waves into the body and reconstructs the images of internal organs based on the strength of the echoes. Ultrasound imaging is considered to be safer, economical and can image the organs in real-time, which makes it widely used diagnostic imaging modality in health-care. Ultrasound imaging covers the broad spectrum of medical diagnostics; these include diagnosis of kidney, liver, pancreas, fetal monitoring, etc. Currently, the diagnosis through ultrasound scanning is clinic-centered, and the patients who are in need of ultrasound scanning has to visit the hospitals for getting the diagnosis. The services of an ultrasound system are constrained to hospitals and did not translate to its potential in remote health-care and point-of-care diagnostics due to its high form factor, shortage of sonographers, low signal to noise ratio, high diagnostic subjectivity, etc. In this thesis, we address these issues with an objective of making ultrasound imaging more reliable to use in point-of-care and remote health-care applications. To achieve the goal, we propose (i) computer-assisted algorithms to improve diagnostic accuracy and assist semi-skilled persons in scanning, (ii) speckle suppression algorithms to improve the diagnostic quality of ultrasound image, (iii) a reliable telesonography framework to address the shortage of sonographers, and (iv) a programmable portable ultrasound scanner to operate in point-of-care and remote health-care applications

Uso eficiente de aritmética redundante en FPGAs

Hasta hace pocos años, la utilización de aritmética redundante en FPGAs había sido descartada por dos razones principalmente. En primer lugar, por el buen rendimiento que ofrecían los sumadores de acarreo propagado, gracias a la lógica de de acarreo que poseían de fábrica y al pequeño tamaño de los operandos en las aplicaciones típicas para FPGAs. En segundo lugar, el excesivo consumo de área que las herramientas de síntesis obtenían cuando mapeaban unidades que trabajan en carrysave. En este trabajo, se muestra que es posible la utilización de aritmética redundante carry-save en FPGAs de manera eficiente, consiguiendo un aumento en la velocidad de operación con un consumo de recursos razonable. Se ha introducido un nuevo formato redundante doble carry-save y se ha demostrado que la manera óptima para la realización de multiplicadores de elevado ancho de palabra es la combinación de multiplicadores empotrados con sumadores carry-save.Till a few years ago, redundant arithmetic had been discarded to be use in FPGA mainly for two reasons. First, the efficient results obtained using carry-propagate adders thanks to the carry-logic embedded in FPGAs and the small sizes of operands in typical FPGA applications. Second, the high number of resources that the synthesis tools utilizes to implement carry-save circuits. In this work, it is demonstrated that carry-save arithmetic can be efficiently used in FPGA, obtaining an important speed improvement with a reasonable area cost. A new redundant format, double carry-save, has been introduced, and the optimal implementation of large size multipliers has been shown based on embedded multipliers and carry-save adders

Architecture d'un processeur dédié aux traitements de signaux ultrasoniques en temps réel en vue d'une intégration sur puce

RÉSUMÉ Cette thèse se rapporte à la conception d’une nouvelle architecture d’un système d’appareils d’imagerie médicale par ultrasons (IMU); nous proposons une architecture matérielle d’un processeur dédié au prétraitement de signaux ultrasoniques en temps réel, qui intègre un cœur (core) de traitement, un module d’interpolation et un module d’assignation de priorités qui permet de partager le bus de données d’une mémoire à faible consommation d’énergie. Ce processeur dédié représente une contribution importante aux efforts visant à l’intégration complète d’un système de prétraitement de signaux ultrasoniques à l’intérieur d’une sonde qui fait partie des appareillages ultrasoniques conventionnels ainsi qu’à la mise en œuvre d’un nouveau type d’appareil d’IMU sans fil. La littérature des deux dernières décennies présente diverses approches visant à miniaturiser la technologie de l’IMU. Plusieurs auteurs proposent des solutions en matière d’intégration des circuits frontaux ou de matérialisation de nouveaux algorithmes de traitement des signaux ultrasoniques. Les efforts de recherche dans ce domaine sont propulsés par l’intérêt grandissant des marchés et par le développement de nouvelles applications qui bénéficient de la miniaturisation de cette technologie. De plus, les performances grandissantes des circuits intégrés programmables tels que les FPGA offrent les caractéristiques appropriées pour la mise en œuvre de nouveaux systèmes d’IMU.----------ABSTRACT This Ph.D. thesis is related to the design of a new architecture of ultrasound medical imaging (UMI) system. We propose a fully hardware-based processor dedicated to real-time ultrasonic signal processing, which incorporates a preprocessing core, a low-power memory, an interpolation unit, and a priority assignment unit. This Ph.D. thesis represents an important contribution towards the complete integration of an ultrasound preprocessing system within the probe and the implementation of a new type of wireless UMI device. During the last two decades, several UMI system miniaturization approaches have been presented in the literature. Some Authors proposed their front-end circuit integration and introduced hardware-based ultrasound signal processing units based on new algorithms. Research efforts in this area are driven by the increasing industrial interest on miniaturized UMI devices and by the development of new applications that benefit from the miniaturization of this technology. Moreover, the increasing performance of programmable circuits, such as FPGA, offers appropriate characteristics for the implementation of new UMI systems. Most UMI system architectures found in the literature are based in whole or in part on a software implementation that uses a central processing unit (CPU) or a digital signal processor (DSP). This software approach provides flexibility and facilitates the implementation of processing algorithms which are becoming ever more effective and complex. However, to provide real-time ultrasound image processing, these systems require high-power consumption or are too large for a complete system integration on a single chip (SoC)

REAL-TIME ELASTOGRAPHY SYSTEMS

Ultrasound elastography is a technique that is often used to detect cancerous tumors and monitor ablation therapy by detecting changes in the stiffness of the underlying tissue. This technique is a computationally expensive due to the extensive searching between two raw ultrasound images, that are called radio frequency images. This thesis explores various methods to accelerate the computation required for the elastography technique to allow use during surgery. This thesis is divided into three parts. We begin by exploring acceleration techniques, including multithreading techniques, asynchronous computing, and acceleration of the graphics processing unit (GPU). Elastography algorithms are often affected by out-of-plane motion due to several external factors, such as hand tremors and incorrect palpation motion, amongst others. In this thesis, we implemented an end-to-end system that integrates an external tracker system to detect the in-plane motion of two radio frequency (RF) data slices. This in-plane detection helps to reduce de-correlated RF slices and produces a consistent elastography output. We also explore the integration of a da Vinci Surgical Robot to provide stable palpation motion during the surgery. The external tracker system suffers from interference due to ferromagnetic materials present in the operation theater in the case of an electromagnetic tracker, while optical and camera-based tracking systems are restricted due to human, object and patient interference in the path of sight and complete or partial occlusion of the tracking sensors. Additionally, these systems must be calibrated to give the position of the tracked objects with respect to the trackers. Although calibration and trackers are helpful for inter-modality registration, we focus on a tracker-less method to determine the in-plane motion of two RF slices. Our technique divides the two input RF images into regions of interest and performs elastography on RF lines that encapsulate those regions of interest. Finally, we implemented the world’s first known five-dimensional ultrasound system. We built the five-dimensional ultrasound system by combining a 3D B-mode volume and a 3D elastography volume visualized over time. A user controlled multi-dimensional transfer function is used to differentiate between the 3D B-mode and the 3D elastography volume

Multichannel Arbitrary Waveform Beamformer Transmitter For Experimental Research Activities Of Ultrasound [beamformer De Transmissão Multicanal De Forma De Onda Arbitrária Para Atividades De Pesquisa Experimental Do Ultrassom]

This paper presents the development of a digital beamformer transmitter system for generation of arbitrary ultrasound waveforms, specifically designed for research purposes. The proposed architecture has 8 independent excitation channels and uses an FPGA device (Field Programmable Gated Array) for electronic control channel generation of ultrasonic acoustic beam transmission. The system allows operation in pulse-echo mode, with pulse repetition rate of excitation between 62.5 Hz and 8 kHz, or single pulse, center frequency between 500 kHz and 20 MHz, excitation voltage between -100 and +100 V, and individual control of amplitude apodization, phase angle and time delay trigger. The mathematical method for determining the digital signals of excitation is presented and validated through practical results for waveform generation with Gaussian profile and center frequency of 20 MHz, in a load formed by a 220 pF capacitor in parallel with a resistor of 1 kΩ. The results show that the proposed flexible and fully programmable architecture, can support the development of new algorithms and sophisticated processing techniques of the transmission beamformer.236667678(2010) Cyclone III Device Handbook I-II. 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