Variability-aware architectures based on hardware redundancy for nanoscale reliable computation

During the last decades, human beings have experienced a significant enhancement in the quality of life thanks in large part to the fast evolution of Integrated Circuits (IC). This unprecedented technological race, along with its significant economic impact, has been grounded on the production of complex processing systems from highly reliable compounding devices. However, the fundamental assumption of nearly ideal devices, which has been true within the past CMOS technology generations, today seems to be coming to an end. In fact, as MOSFET technology scales into nanoscale regime it approaches to fundamental physical limits and starts experiencing higher levels of variability, performance degradation, and higher rates of manufacturing defects. On the other hand, ICs with increasing number of transistors require a decrease in the failure rate per device in order to maintain the overall chip reliability. As a result, it is becoming increasingly important today the development of circuit architectures capable of providing reliable computation while tolerating high levels of variability and defect rates. The main objective of this thesis is to analyze and propose new fault-tolerant architectures based on redundancy for future technologies. Our research is founded on the principles of redundancy established by von Neumann in the 1950s and extends them to three new dimensions: 1. Heterogeneity: Most of the works on fault-tolerant architectures based on redundancy assume homogeneous variability in the replicas like von Neumann's original work. Instead, we explore the possibilities of redundancy when heterogeneity between replicas is taken into account. In this sense, we propose compensating mechanisms that select the weighting of the redundant information to maximize the overall reliability. 2. Asynchrony: Each of the replicas of a redundant system may have associated different processing delays due to variability and degradation; especially in future nanotechnologies. If we design our system to work locally in asynchronous mode then we may consider different voting policies to deal with the redundant information. Depending on how many replicas we collect before taking a decision we can obtain different trade-off between processing delay and reliability. We propose a mechanism for providing these facilities and analyze and simulate its operation. 3. Hierarchy: Finally, we explore the possibilities of redundancy applied at different hierarchy layers of complex processing systems. We propose to distribute redundancy across the various hierarchy layers and analyze the benefits that can be obtained. Drawing on the scenario of future ICs technologies, we push the concept of redundancy to its fullest expression through the study of realistic nano-device architectures. Most of the redundant architectures considered so far do not face properly the era of Terascale Computing and the nanotechnology trends. Since von Neumann applied for the first time redundancy at electronic circuits, never until now effects as common in nanoelectronics as degradation and interconnection failures have been treated directly from the standpoint of redundancy. In this thesis we address in a comprehensive manner the reliability of digital processing systems in the upcoming technology generations

A Review on Key Issues and Challenges in Devices Level MEMS Testing

The present review provides information relevant to issues and challenges in MEMS testing techniques that are implemented to analyze the microelectromechanical systems (MEMS) behavior for specific application and operating conditions. MEMS devices are more complex and extremely diverse due to the immersion of multidomains. Their failure modes are distinctive under different circumstances. Therefore, testing of these systems at device level as well as at mass production level, that is, parallel testing, is becoming very challenging as compared to the IC test, because MEMS respond to electrical, physical, chemical, and optical stimuli. Currently, test systems developed for MEMS devices have to be customized due to their nondeterministic behavior and complexity. The accurate measurement of test systems for MEMS is difficult to quantify in the production phase. The complexity of the device to be tested required maturity in the test technique which increases the cost of test development; this practice is directly imposed on the device cost. This factor causes a delay in time-to-market

A Review on Key Issues and Challenges in Devices Level MEMS Testing

The present review provides information relevant to issues and challenges in MEMS testing techniques that are implemented to analyze the microelectromechanical systems (MEMS) behavior for specific application and operating conditions. MEMS devices are more complex and extremely diverse due to the immersion of multidomains. Their failure modes are distinctive under different circumstances. Therefore, testing of these systems at device level as well as at mass production level, that is, parallel testing, is becoming very challenging as compared to the IC test, because MEMS respond to electrical, physical, chemical, and optical stimuli. Currently, test systems developed for MEMS devices have to be customized due to their nondeterministic behavior and complexity. The accurate measurement of test systems for MEMS is difficult to quantify in the production phase. The complexity of the device to be tested required maturity in the test technique which increases the cost of test development; this practice is directly imposed on the device cost. This factor causes a delay in time-to-market

From RF-Microsystem Technology to RF-Nanotechnology

The RF microsystem technology is believed to introduce a paradigm switch in the wireless revolution. Although only few companies are to date doing successful business with RF-MEMS, and on a case-by-case basis, important issues need yet to be addressed in order to maximize yield and performance stability and hence, outperform alternative competitive technologies (e.g. ferroelectric, SoS, SOI,…). Namely the behavior instability associated to: 1) internal stresses of the free standing thin layers (metal and/or dielectric) and 2) the mechanical contact degradation, be it ohmic or capacitive, which may occur due to low forces, on small areas, and while handling severe current densities.The investigation and understanding of these complex scenario, has been the core of theoretical and experimental investigations carried out in the framework of the research activity that will be presented here. The reported results encompass activities which go from coupled physics (multiphysics) modeling, to the development of experimental platforms intended to tackles the underlying physics of failure. Several original findings on RF-MEMS reliability in particular with respect to the major failure mechanisms such as dielectric charging, metal contact degradation and thermal induced phenomena have been obtained. The original use of advanced experimental setup (surface scanning microscopy, light interferometer profilometry) has allowed the definition of innovative methodology capable to isolate and separately tackle the different degradation phenomena under arbitrary working conditions. This has finally permitted on the one hand to shed some light on possible optimization (e.g. packaging) conditions, and on the other to explore the limits of microsystem technology down to the nanoscale. At nanoscale indeed many phenomena take place and can be exploited to either enhance conventional functionalities and performances (e.g. miniaturization, speed or frequency) or introduce new ones (e.g. ballistic transport). At nanoscale, moreover, many phenomena exhibit their most interesting properties in the RF spectrum (e.g. micromechanical resonances). Owing to the fact that today’s minimum manufacturable features have sizes comparable with the fundamental technological limits (e.g. surface roughness, metal grain size, …), the next generation of smart systems requires a switching paradigm on how new miniaturized components are conceived and fabricated. In fact endowed by superior electrical and mechanical performances, novel nanostructured materials (e.g. carbon based, as carbon nanotube (CNT) and graphene) may provide an answer to this endeavor. Extensively studied in the DC and in the optical range, the studies engaged in LAAS have been among the first to target microwave and millimiterwave transport properties in carbon-based material paving the way toward RF nanodevices. Preliminary modeling study performed on original test structures have highlighted the possibility to implement novel functionalities such as the coupling between the electromagnetic (RF) and microelectromechanical energy in vibrating CNT (toward the nanoradio) or the high speed detection based on ballistic transport in graphene three-terminal junction (TTJ). At the same time these study have contributed to identify the several challenges still laying ahead such as the development of adequate design and modeling tools (ballistic/diffusive, multiphysics and large scale factor) and practical implementation issues such as the effects of material quality and graphene-metal contact on the electrical transport. These subjects are the focus of presently on-going and future research activities and may represent a cornerstone of future wireless applications from microwave up to the THz range

Fault modelling and accelerated simulation of integrated circuits manufacturing defects under process variation

As silicon manufacturing process scales to and beyond the 65-nm node, process variation can no longer be ignored. The impact of process variation on integrated circuit performance and power has received significant research input. Variation-aware test, on the other hand, is a relatively new research area that is currently receiving attention worldwide.Research has shown that test without considering process variation may lead to loss of test quality. Fault modelling and simulation serve as a backbone of manufacturing test. This thesis is concerned with developing efficient fault modelling techniques and simulation methodologies that take into account the effect of process variation on manufacturing defects with particular emphasis on resistive bridges and resistive opens.The first contribution of this thesis addresses the problem of long computation time required to generate logic fault of resistive bridges under process variation by developing a fast and accurate modelling technique to model logic fault behaviour of resistive bridges.The new technique is implemented by employing two efficient voltage calculation algorithms to calculate the logic threshold voltage of driven gates and critical resistance of a fault-site to enable the computation of bridge logic faults without using SPICE. Simulation results show that the technique is fast (on average 53 times faster) and accurate (worst case is 2.64% error) when compared with HSPICE. The second contribution analyses the complexity of delay fault simulation of resistive bridges to reduce the computation time of delay fault when considering process variation. An accelerated delay fault simulation methodology of resistive bridges is developed by employing a three-step strategy to speed up the calculation of transient gate output voltage which is needed to accurately compute delay faults. Simulation results show that the methodology is on average 17.4 times faster, with 5.2% error in accuracy, when compared with HSPICE. The final contribution presents an accelerated simulation methodology of resistive opens to address the problem of long simulation time of delay fault when considering process variation. The methodology is implemented by using two efficient algorithms to accelerate the computation of transient gate output voltage and timing critical resistance of an open fault-site. Simulation results show that the methodology is on average up to 52 times faster than HSPICE, with 4.2% error in accuracy

Defect Assisted Growth of Copper-Silicide Nanostructures on Si(100) and Si(111)

As the dimensions of the smallest feature on the integrated circuit has minia-turized into the range of tens of nanometers, patterning of highly ordered nanos-tructures with tunable size and shape in large scale on the surface of substrate is highly demanding and increasingly challenges the limits of nanolithography. To over-come the conventional lithographic limitations, self assembled methods have been explored. While strain driven self assembly is widely viewed as a promising technique for patterning at the nanoscale, to follow this approach and create structures in a desired manner, a reliable means to engineer and characterize the shape and sizes of nanostructures during self assembly is essential. The work presented here describes a detailed analysis of the morphological and compositional evolution of patterns in Cu3Si strain-driven self assembles. The first project described in this thesis is the fabrication of self assembled copper silicide nanostructures on SiO2/Si(111) and SiO2/Si(100) with electron beam evaporation in ultrahigh vacuum. The copper silicide growth was determined to be defect assisted. In order to create defect sites or voids at the surface, the SiO2/Si substrates in this work were annealed at 500◦C for 10-12 hours in a vacuum sys-tem prior to the deposition of Cu. The development of these nucleation centers or voids at the surface is discussed along with the deposition of Cu at low temperatures (T \u3c 450◦C) and the deposition of Cu and growth of nanostructures in an optimal temperature range (450◦C \u3c T \u3c 600◦C). The variation in the density of voids at the sample surfaces was investigated with SEM-EDS and XRD techniques. Copper silicide phase and orientation of nanostructures were investigated with SEM-EDAX techniques. For the growth of Cu3Si nanostructures on SiO2/Si(111), equilateral tri-angles of various sizes were found to grow up to a critical size, beyond which the shape transitioned from equilateral triangular to trapezoid. For Cu3Si nanostruc-tures on the SiO2/Si(100) surface, square islands were found to grow up to a critical size, beyond which rectangular islands and long nanowires were formed. A growth mechanisms for Cu3Si nanostructures based on the strain induced shape transition growth model is discussed. The second project discussed in this thesis is the nanopatterning of self as-sembled copper silicide nanostructures on SiO2/Si(111) and SiO2/Si(100) with highly charged ion beams (HCIs) of argon. Since the void creation at surface using the ther-mal annealing technique requires long times, we investigated the use of highly charge ion beams to induce defect sites on the surface of the substrate. Arq+ ion beams of varying fluence and charge state (q=1,4,8) were used to produce nucleation centers or voids at the surface of SiO2/Si substrates. This approach could provide an alternative method for probing the sputter yields of HCI irradiated oxides. The deposition of Cu and the growth of nanostructures at an optimal temperature of 600◦C are discussed. The variation in the density and orientation of Cu3Si nanostructures as a function of HCI charge state and fluence were investigated with the SEM-EDS technique. For the growth of Cu3Si nanostructures on SiO2/p-Si(111) and on SiO2/p-Si(100) surfaces, square islands have been found to grow up to a critical size, beyond which rectangular islands and long nanowires were formed. In general, the growth results were similar to the previous study. However, the size and hence the growth rate was significantly longer. The final project presented in this thesis is modification of the surface prop-erties of polycarbonate with HCIs. Polycarbonate (PC, Lexan) has many industrial applications because of its excellent transparency and high impact resistance. How-ever, PC requires a surface modification to improve adhesion for metallization and optical applications. The surface of PC samples were irradiated with highly charged ion beams of argon and oxygen in order to understand the role of low energy HCIs on the surface modification. Surface characterization of PC prior to and after HCI irradiation was performed using the XPS technique. Chain scission and cross linking were determined to occur during the HCI polymer interaction. The change in the relative intensities of C-C,C-O and C=O functional groups with HCI species, charge state and fluence were discussed. An increase in the relative intensities of C-O, C=O and a decrease in C-C bond intensities were discussed in terms of potential energy dependent sputtering

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

연성 및 생재흡수성 전자소자용 비휘발성 메모리 소자와 집적센서 구현

학위논문 (박사)-- 서울대학교 대학원 : 화학생물공학부, 2015. 8. 김대형.Over years, major advances in healthcare have been made through research in the fields of nanomaterials and microelectronics technologies. However, the mechanical and geometrical constraints inherent in the standard forms of rigid electronics have imposed challanges of unique integration and therapeutic delivery in non-invasive and minimally invasive medical devices. Here, we describe two types of multifunctional electronic systems. The first type is wearable-on-the-skin systems that address the challenges via monolithic integration of nanomembranes fabricated by top-down approach, nanotubes and nanoparticles assembled by bottom-up strategies, and stretchable electronics on tissue-like polymeric substrate. The system consists of physiological sensors, non-volatile memory, logic gates, and drug-release actuators. Some quantitative analyses on the operation of each electronics, mechanics, heat-transfer, and drug-diffusion characteristic validated their system-level multi-functionalities. The second type is a bioresorbable electronic stent with drug-infused functionalized nanoparticles that takes flow sensing, temperature monitoring, data storage, wireless power/data transmission, inflammation suppression, localized drug delivery, and photothermal therapy. In vivo and ex vivo animal experiments as well as in vitro cell researches demonstrate its unrecognized potential for bioresorbable electronic implants coupled with bioinert therapeutic nanoparticles in the endovascular system. As demonstrations of these technologies, we herein highlight two representative examples of multifunctional systems in order of increasing degree of invasiveness: electronically enabled wearable patch and endovascular electronic stent that incorporate onboard physiological monitoring, data storage, and therapy under moist and mechanically rigorous conditions.Contents Abstract Chapter 1. Introduction 1.1 Organic flexible and wearable electronics.................................................. 1 1.2 Inorganic flexible and wearable electronics............................................... 14 1.3 Flexible non-volatile memory devices.......................................................... 25 1.4 Bioresorbable materials and devices........................................................... 34 References Chapter 2. Multifunctional wearable devices for diagnosis and therapy of movement disorders 2.1 Introduction ................................................................................. 45 2.2 Experimental Section ......................................................................... 49 2.3 Result and Discussion ........................................................................ 65 2.4 Conclusion ................................................................................... 95 References Chapter 3. Stretchable Carbon Nanotube Charge-Trap Floating-Gate Memory and Logic Devices for Wearable Electronics 3.1 Introduction ................................................................................ 101 3.2 Experimental Section ........................................................................ 104 3.3 Result and Discussion ....................................................................... 107 3.4 Conclusion .................................................................................. 138 References Chapter 4. Bioresorbable Electronic Stent Integrated with Therapeutic Nanoparticles for Endovascular Diseases 4.1 Introduction ................................................................................ 148 4.2 Experimental Section ........................................................................ 151 4.3 Result and Discussion ....................................................................... 173 4.4 Conclusion .................................................................................. 219 References 국문 초록 (Abstract in Korean) .................................................................. 230Docto

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book