Low-Voltage Analog Circuit Design Using the Adaptively Biased Body-Driven Circuit Technique

The scaling of MOSFET dimensions and power supply voltage, in conjunction with an increase in system- and circuit-level performance requirements, are the most important factors driving the development of new technologies and design techniques for analog and mixed-signal integrated circuits. Though scaling has been a fact of life for analog circuit designers for many years, the approaching 1-V and sub-1-V power supplies, combined with applications that have increasingly divergent technology requirements, means that the analog and mixed-signal IC designs of the future will probably look quite different from those of the past. Foremost among the challenges that analog designers will face in highly scaled technologies are low power supply voltages, which limit dynamic range and even circuit functionality, and ultra-thin gate oxides, which give rise to significant levels of gate leakage current. The goal of this research is to develop novel analog design techniques which are commensurate with the challenges that designers will face in highly scaled CMOS technologies. To that end, a new and unique body-driven design technique called adaptive gate biasing has been developed. Adaptive gate biasing is a method for guaranteeing that MOSFETs in a body-driven simple current mirror, cascode current mirror, or regulated cascode current source are biased in saturation—independent of operating region, temperature, or supply voltage—and is an enabling technology for high-performance, low-voltage analog circuits. To prove the usefulness of the new design technique, a body-driven operational amplifier that heavily leverages adaptive gate biasing has been developed. Fabricated on a 3.3-V/0.35-μm partially depleted silicon-onv-insulator (PD-SOI) CMOS process, which has nMOS and pMOS threshold voltages of 0.65 V and 0.85 V, respectively, the body-driven amplifier displayed an open-loop gain of 88 dB, bandwidth of 9 MHz, and PSRR greater than 50 dB at 1-V power supply

Achieving rail-to-rail input operation using level-shift multiplexing technique for all CMOS op-amps

This paper presents a new design approach which can convert any CMOS operational amplifiers to have rail-to-rail common-mode input capability by utilizing few additional hardware elements. The proposed circuit can operate over a wide range of supply voltages from 1-volt to the maximum allowed for the CMOS process, without degrading the ac and dc performances of the amplifier in question over the rail-to-rail operation

A Survey of Non-conventional Techniques for Low-voltage Low-power Analog Circuit Design

Designing integrated circuits able to work under low-voltage (LV) low-power (LP) condition is currently undergoing a very considerable boom. Reducing voltage supply and power consumption of integrated circuits is crucial factor since in general it ensures the device reliability, prevents overheating of the circuits and in particular prolongs the operation period for battery powered devices. Recently, non-conventional techniques i.e. bulk-driven (BD), floating-gate (FG) and quasi-floating-gate (QFG) techniques have been proposed as powerful ways to reduce the design complexity and push the voltage supply towards threshold voltage of the MOS transistors (MOST). Therefore, this paper presents the operation principle, the advantages and disadvantages of each of these techniques, enabling circuit designers to choose the proper design technique based on application requirements. As an example of application three operational transconductance amplifiers (OTA) base on these non-conventional techniques are presented, the voltage supply is only ±0.4 V and the power consumption is 23.5 µW. PSpice simulation results using the 0.18 µm CMOS technology from TSMC are included to verify the design functionality and correspondence with theory

A SigmaDelta modulator for digital hearing instruments using 0.18 mum CMOS technology.

This thesis develops the design methodology for a low-voltage low-power SigmaDelta Modulator, realized using a switched op-amp technique that can be used in a hearing instrument. Switched op-amp implementation allows scaling down the design to the latest CMOS technology. A single-loop second-order SigmaDelta Modulator topology is chosen. The modulator circuit features reduced complexity, area reduction and low conversion energy. The modulator has a sampling rate of 8.2 MHz with an over-sampling ratio (OSR) of 256 to provide an audio bandwidth of 16 kHz. The modulator is implemented in a 0.18 mum digital CMOS technology with metal-to-metal sandwich structure capacitors. The modulator operates with a supply voltage of 1.8 V. The active area is 0.403 mm2. The modulator achieves a 98 dB signal-to-noise-and-distortion ratio (SNDR) and a 100 dB dynamic range (DR) at a Nyquist conversion rate of 32 kHz and consumes 1321 muW with a joule/conversion figure of merit equal to 161 x 10-12 J/s. The design methodology is developed through the extensive use of simulation tools. The behaviour simulation is carried out using Matlab/SIMULINK while circuits are simulated with Hspice using the Cadence design tools. Full-custom layout for the analog and the digital circuits is performed using the Cadence design tool. Post-processing simulation of the extracted modulator with parasitic verifies that results meet the requirements. The design has been sent to CMC for fabrication. Source: Masters Abstracts International, Volume: 43-03, page: 0947. Adviser: W. C. Miller. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004

Pseudo-three-stage Miller op-amp with enhanced small-signal and large-signal performance

A simple technique to implement highly power efficient class AB-AB Miller op-amps is presented in this paper. It uses a composite input stage with resistive local common mode feedback that provides class AB operation to the input stage and essentially enhances the op-amp's effective transconductance gain, the dc open-loop gain, the gain-bandwidth product, and slew rate with just moderate increase in power dissipation. The experimental results of op-amps in strong inversion and subthreshold fabricated in a 130-nm standard CMOS technology validate the proposed approach. The op-amp has 9 V·pF/μs·μW large-signal figure of merit (FOM) and 17 MHz · pF/μW small-signal FOM with 1.2-V supply voltage. In subthreshold, the op-amp has 10 V · pF/μs · μW large-signal FOM and 92 MHz · pF/μW small-signal FOM with 0.5-V supply voltage.This work was supported by Grant TEC2016-80396- C2-R (AEI/FEDER)

Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110

ANALYSIS AND DESIGN OF AN ULTRA-LOW POWER LOW-NOISE DTMOS BASED INSTRUMENTATION AMPLIFIER APPLIED TO THE PHYSIOLOGICAL SIGNAL ACQUISITION SYSTEM

With the rapid development of Internet of Things (IoT) technology and the popularity of portable devices, portable medical devices will become widely available soon. Physiological signal monitoring sensors are widely used for personal health management and long-term healthcare monitoring, especially for preventing acute illnesses and chronic disease monitoring for pediatric and elderly. Physiological signal monitoring sensors have the ability to monitor people's behavior in real-time for various daily activities, such as physiological signals that exhibit different waveforms and amplitudes when sleeping and awake. The real-time collected signals can be frequently compared to medical databases to detect abnormal health data for preventive healthcare. Therefore, an accurate and error-free system that provides high-quality monitoring of physiological signals is very important. Typically, an instrumentation amplifier (IA) is used for high accurate acquisition and amplification within this system. An IA with excellent performance gives patients safer health conditions and allows patients to have better health protection.This work introduces an ultra-low-power instrumentation amplifier operating at sub-0.4V voltage. Using dynamic threshold voltage MOSFET (DTMOS). The DTMOS reduces threshold voltage further and increases the driven current while the device is operating. Therefore, the DTMOS-based folded-cascode has been chosen, resulting in an increases the common-mode rejection ratio (CMRR) of the circuit while increasing the output signal swing compared over conventional topologies. The IA takes the benefit of the rail-to-rail common-mode feedback circuit and chopping to reduce flicker noise and DC offset. Reducing the chip area and power consumption leads to the output signal's high signal-to-noise ratio (SNR). The post-simulation shows that the circuit archives 45dB gain, DC to 2.07KHz operating bandwidth, and 0.8μW total power consumption. The simulated CMRR is 103dB, with 80dB power supply rejection ratio (PSRR). The simulated input reference noise is 140nV/√Hz (@100Hz) with 7.27 Noise Efficiency Factor (NEF).Keywords: Instrumentation Amplifier, DTMOS, rail-to-rail, chopping, clock boosting switch, physiological acquisition, bio-medical application

Complementary Bodydriving - A Low-voltage Analog Circuit Technique Realized In 0.35um SOI Process

This thesis presents a study of several analog circuit primitives that utilize the body terminal as a signal port to achieve low-voltage operation and high performance. Several issues relating to low-voltage applications as well as the trends of technology scaling in the near future are presented. Principles of the body-driven transistor for both PMOS and NMOS in PDSOI technology are described, and critical design considerations are discussed. The design of low-voltage analog primitives (cascode current mirror and differential pair) are described and analyzed in detail. A discussion of the design and analysis of a 4-quadrant analog multiplier is also presented. Prototyping and testing procedures are discussed and the results of the prototyped circuits are evaluated. Finally, a summary of the work is presented along with insights gained toward future research