An Approach for Estimating the Reliability of IGBT Power Modules in Electrified Vehicle Traction Inverters

The reliability analysis of traction inverters is of great interest due to the use of new semi-conductor devices and inverter topologies in electric vehicles (EVs). Switching devices in the inverter are the most vulnerable component due to the electrical, thermal and mechanical stresses based on various driving conditions. Accurate stress analysis of power module is imperative for development of compact high-performance inverter designs with enhanced reliability. Therefore, this paper presents an inverter reliability estimation approach using an enhanced power loss model developed considering dynamic and transient influence of power semi-conductors. The temperature variation tracking has been improved by incorporating power module component parameters in an LPTN model of the inverter. A 100 kW EV grade traction inverter is used to validate the developed mathematical models towards estimating the inverter performance and subsequently, predicting the remaining useful lifetime of the inverter against two commonly used drive cycles

Non-adiabatic Electron Pumping through Interacting Quantum Dots

We study non-adiabatic charge pumping through single-level quantum dots taking into account Coulomb interactions. We show how a truncated set of equations of motion can be propagated in time by means of an auxiliary-mode expansion. This formalism is capable of treating the time-dependent electronic transport for arbitrary driving parameters. We verify that the proposed method describes very precisely the well-known limit of adiabatic pumping through quantum dots without Coulomb interactions. As an example we discuss pumping driven by short voltage pulses for various interaction strengths. Such finite pulses are particular suited to investigate transient non-adiabatic effects, which may be also important for periodic drivings, where they are much more difficult to reveal.Comment: 11 pages, 4 figure

Analysis of marine container terminal gate congestion, truck waiting cost, and system optimization

As world container volume continues to grow and the introduction of 12,000 TEUs plus containerships into major trade routes, the port industry is under pressure to deal with the ever increasing freight volume. Gate congestion at marine container terminal is considered a major issue facing truckers who come to the terminal for container pickup and delivery. Harbor truckers operate in a very competitive environment; they are paid by trip, not by the hours they drive. Gate congestion is not only detrimental to their economic well-being, but also causes environmental pollution. This thesis applies a multi-server queuing model to analyze marine terminal gate congestion and quantify truck waiting cost. In addition, an optimization model is developed to minimize gate system cost. Extensive data collection includes field observations and online camera observation and terminal day-to-day operation records. Comprehensive data analysis provides a solid foundation to support the development of the optimization model. The queuing analysis indicates that there is a substantial truck waiting cost incurred during peak season. Three optimization alternatives are explored. The results prove that optimization by appointment is the most effective way to reduce gate congestion and improve system efficiency. Lastly, it is the recommendation to use the combination of optimization by appointment and productivity improvement to mitigate terminal gate congestion and accommodate the ever growing container volume

Statistical circuit simulations - from ‘atomistic’ compact models to statistical standard cell characterisation

This thesis describes the development and application of statistical circuit simulation methodologies to analyse digital circuits subject to intrinsic parameter fluctuations. The specific nature of intrinsic parameter fluctuations are discussed, and we explain the crucial importance to the semiconductor industry of developing design tools which accurately account for their effects. Current work in the area is reviewed, and three important factors are made clear: any statistical circuit simulation methodology must be based on physically correct, predictive models of device variability; the statistical compact models describing device operation must be characterised for accurate transient analysis of circuits; analysis must be carried out on realistic circuit components. Improving on previous efforts in the field, we posit a statistical circuit simulation methodology which accounts for all three of these factors. The established 3-D Glasgow atomistic simulator is employed to predict electrical characteristics for devices aimed at digital circuit applications, with gate lengths from 35 nm to 13 nm. Using these electrical characteristics, extraction of BSIM4 compact models is carried out and their accuracy in performing transient analysis using SPICE is validated against well characterised mixed-mode TCAD simulation results for 35 nm devices. Static d.c. simulations are performed to test the methodology, and a useful analytic model to predict hard logic fault limitations on CMOS supply voltage scaling is derived as part of this work. Using our toolset, the effect of statistical variability introduced by random discrete dopants on the dynamic behaviour of inverters is studied in detail. As devices scaled, dynamic noise margin variation of an inverter is increased and higher output load or input slew rate improves the noise margins and its variation. Intrinsic delay variation based on CV/I delay metric is also compared using ION and IEFF definitions where the best estimate is obtained when considering ION and input transition time variations. Critical delay distribution of a path is also investigated where it is shown non-Gaussian. Finally, the impact of the cell input slew rate definition on the accuracy of the inverter cell timing characterisation in NLDM format is investigated

Design of variation-tolerant synchronizers for multiple clock and voltage domains

PhD ThesisParametric variability increasingly affects the performance of electronic circuits as the fabrication technology has reached the level of 32nm and beyond. These parameters may include transistor Process parameters (such as threshold voltage), supply Voltage and Temperature (PVT), all of which could have a significant impact on the speed and power consumption of the circuit, particularly if the variations exceed the design margins. As systems are designed with more asynchronous protocols, there is a need for highly robust synchronizers and arbiters. These components are often used as interfaces between communication links of different timing domains as well as sampling devices for asynchronous inputs coming from external components. These applications have created a need for new robust designs of synchronizers and arbiters that can tolerate process, voltage and temperature variations. The aim of this study was to investigate how synchronizers and arbiters should be designed to tolerate parametric variations. All investigations focused mainly on circuit-level and transistor level designs and were modeled and simulated in the UMC90nm CMOS technology process. Analog simulations were used to measure timing parameters and power consumption along with a “Monte Carlo” statistical analysis to account for process variations. Two main components of synchronizers and arbiters were primarily investigated: flip-flop and mutual-exclusion element (MUTEX). Both components can violate the input timing conditions, setup and hold window times, which could cause metastability inside their bistable elements and possibly end in failures. The mean-time between failures is an important reliability feature of any synchronizer delay through the synchronizer. The MUTEX study focused on the classical circuit, in addition to a number of tolerance, based on increasing internal gain by adding current sources, reducing the capacitive loading, boosting the transconductance of the latch, compensating the existing Miller capacitance, and adding asymmetry to maneuver the metastable point. The results showed that some circuits had little or almost no improvements, while five techniques showed significant improvements by reducing τ and maintaining high tolerance. Three design approaches are proposed to provide variation-tolerant synchronizers. wagging synchronizer proposed to First, the is significantly increase reliability over that of the conventional two flip-flop synchronizer. The robustness of the wagging technique can be enhanced by using robust τ latches or adding one more cycle of synchronization. The second approach is the Metastability Auto-Detection and Correction (MADAC) latch which relies on swiftly detecting a metastable event and correcting it by enforcing the previously stored logic value. This technique significantly reduces the resolution time down from uncertain synchronization technique is proposed to transfer signals between Multiple- Voltage Multiple-Clock Domains (MVD/MCD) that do not require conventional level-shifters between the domains or multiple power supplies within each domain. This interface circuit uses a synchronous set and feedback reset protocol which provides level-shifting and synchronization of all signals between the domains, from a wide range of voltage-supplies and clock frequencies. Overall, synchronizer circuits can tolerate variations to a greater extent by employing the wagging technique or using a MADAC latch, while MUTEX tolerance can suffice with small circuit modifications. Communication between MVD/MCD can be achieved by an asynchronous handshake without a need for adding level-shifters.The Saudi Arabian Embassy in London, Umm Al-Qura University, Saudi Arabi

Power Reductions with Energy Recovery Using Resonant Topologies

The problem of power densities in system-on-chips (SoCs) and processors has become more exacerbated recently, resulting in high cooling costs and reliability issues. One of the largest components of power consumption is the low skew clock distribution network (CDN), driving large load capacitance. This can consume as much as 70% of the total dynamic power that is lost as heat, needing elaborate sensing and cooling mechanisms. To mitigate this, resonant clocking has been utilized in several applications over the past decade. An improved energy recovering reconfigurable generalized series resonance (GSR) solution with all the critical support circuitry is developed in this work. This LC resonant clock driver is shown to save about 50% driver power (\u3e40% overall), on a 22nm process node and has 50% less skew than a non-resonant driver at 2GHz. It can operate down to 0.2GHz to support other energy savings techniques like dynamic voltage and frequency scaling (DVFS). As an example, GSR can be configured for the simpler pulse series resonance (PSR) operation to enable further power saving for double data rate (DDR) applications, by using de-skewing latches instead of flip-flop banks. A PSR based subsystem for 40% savings in clocking power with 40% driver active area reduction xii is demonstrated. This new resonant driver generates tracking pulses at each transition of clock for dual edge operation across DVFS. PSR clocking is designed to drive explicit-pulsed latches with negative setup time. Simulations using 45nm IBM/PTM device and interconnect technology models, clocking 1024 flip-flops show the reductions, compared to non-resonant clocking. DVFS range from 2GHz/1.3V to 200MHz/0.5V is obtained. The PSR frequency is set \u3e3× the clock rate, needing only 1/10th the inductance of prior-art LC resonance schemes. The skew reductions are achieved without needing to increase the interconnect widths owing to negative set-up times. Applications in data circuits are shown as well with a 90nm example. Parallel resonant and split-driver non-resonant configurations as well are derived from GSR. Tradeoffs in timing performance versus power, based on theoretical analysis, are compared for the first time and verified. This enables synthesis of an optimal topology for a given application from the GSR

Characterization Methodology, Modeling, and Converter Design for 600 V Enhancement-Mode GaN FETs

Gallium Nitride (GaN) power devices are an emerging technology that have only become available commercially in the past few years. This new technology enables the design of converters at higher frequencies and efficiencies than those achievable with conventional Si devices. This dissertation reviews the unique characteristics, commercial status, and design challenges that surround GaN FETs, in order to provide sufficient background to potential GaN-based converter designers.Methodology for experimentally characterizing a GaN FET was also presented, including static characterization with a curve tracer and impedance analyzer, as well as dynamic characterization in a double pulse test setup. This methodology was supplemented by additional tests to determine losses caused by Miller-induced cross talk, and the tradeoff between these losses and overlap losses was studied for one example device.Based on analysis of characterization results, a simplified model was developed to describe the overall switching behavior and some unique features of the device. The impact of the Miller effect during the turn-on transient was studied, as well as the dynamic performance of GaN at elevated temperature.Furthermore, solutions were proposed for several key design challenges in GaN-based converters. First, a driver-integrated overcurrent and short-circuit protection scheme was developed, based on the relationship between gate voltage and drain current in GaN gate injection transistors. Second, the limitations on maximum utilization of current and voltage in a GaN FET were studied, particularly the voltage overshoots following turn-on and turn-off switching transients, and the effective cooling of GaN FETs in higher power operation. A thermal design was developed for heat extraction from bottom-cooled surface-mount devices. These solutions were verified in a GaN-based full-bridge single-phase inverter

A Comparison of Emissions-Reduction Strategies to Improve Livability in Freight-Centric Communities

In 2009, the U.S. Department of Transportation, the U.S. Environmental Protection Agency, and the U.S. Department of Housing and Urban Development entered into an interagency “Partnership for Sustainable Communities” to cooperatively increase transportation mode choices while reducing transportation costs, protecting the environment, and providing greater access to affordable housing through the incorporation of six principals of livability (U.S. Department of Transportation, 2014a). This study focuses on strategies to reduce vehicle emissions and improve livability along the Lamar Corridor in Memphis, Tennessee, a location that was designated by the U.S. Government in 2010 as an area to be targeted for livability improvements (Daniels & Meeks, 2010). The results of this study indicate that a common method to reduce emissions at freight terminals, a typical facility along the Lamar Corridor, may actually increase emissions along the corridor itself. Additionally, specific emphasis on the use of alternative fuels as a method to reduce emissions may be warranted