1,054 research outputs found
Cost modelling and concurrent engineering for testable design
This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.As integrated circuits and printed circuit boards increase in complexity, testing becomes a major cost factor of the design and production of the complex devices. Testability has to be considered during the design of complex electronic systems, and automatic test systems have to be used in order to facilitate the test. This fact is now widely accepted in industry. Both design for testability and the usage of automatic test systems aim at reducing the cost of production testing or, sometimes, making it possible at all. Many design for testability methods and test systems are available which can be configured into a production test strategy, in order to achieve high quality of the final product. The designer has to select from the various options for creating a test strategy, by maximising the quality and minimising the total cost for the electronic system.
This thesis presents a methodology for test strategy generation which is based on consideration of the economics during the life cycle of the electronic system. This methodology is a concurrent engineering approach which takes into account all effects of a test strategy on the electronic system during its life cycle by evaluating its related cost. This objective methodology is used in an original test strategy planning advisory system, which allows for test strategy planning for VLSI circuits as well as for digital electronic systems.
The cost models which are used for evaluating the economics of test strategies are described in detail and the test strategy planning system is presented. A methodology for making decisions which are based on estimated costing data is presented. Results of using the cost models and the test strategy planning system for evaluating the economics of test strategies for selected industrial designs are presented
Verification and validation in software product line engineering
Verification and Validation (V&V) is currently performed during application development for many systems, especially safety-critical and mission-critical systems. However, the V&V process has been limited to single system development. This dissertation describes the extension of V&V from an individual application system to a product line of systems that are developed within an architecture-based software engineering environment.;In traditional V&V, the system provides the context under which the software will be evaluated, and V&V activities occur during all phases of the system development lifecycle. The transition to a product line approach to development removes the individual system as the context for evaluation, and introduces activities that are not directly related to a specific system. This dissertation presents an approach to V&V of software product lines that uses the domain model and the domain architecture as the context for evaluation, and enables V&V to be performed throughout the modified lifecycle introduced by domain engineering.;This dissertation presents three advances that assist in the adaptation of V&V from single application systems to a product line of systems. The first is a framework for performing V&V that includes the activities of traditional application-level V&V, and extends these activities into domain engineering and into the transition between domain engineering and application engineering. The second is a detailed method to extend the crucial V&V activity of criticality analysis from single system development to a product line of systems. The third advance is an approach to enable formal reasoning, which is needed for high assurance systems, on systems that are based on commercial-off-the-shelf (COTS) products
Investigations into the feasibility of an on-line test methodology
This thesis aims to understand how information coding and the protocol that it
supports can affect the characteristics of electronic circuits. More specifically, it
investigates an on-line test methodology called IFIS (If it Fails It Stops) and its
impact on the design, implementation and subsequent characteristics of circuits
intended for application specific lC (ASIC) technology.
The first study investigates the influences of information coding and protocol on the
characteristics of IFIS systems. The second study investigates methods of circuit
design applicable to IFIS cells and identifies the· technique possessing the
characteristics most suitable for on-line testing. The third study investigates the
characteristics of a 'real-life' commercial UART re-engineered using the techniques
resulting from the previous two studies. The final study investigates the effects of the
halting properties endowed by the protocol on failure diagnosis within IFIS systems.
The outcome of this work is an identification and characterisation of the factors that
influence behaviour, implementation costs and the ability to test and diagnose IFIS
designs
NEW ALGORITHM FOR BEHAVIOURAL TEST GENERATION
Significant efforts of the test design community have addressed the development of high
level test generation algorithms in the last decade. The main problem originates in the
insufficiently low gate level fault coverage of test sets generated at the behavioural or
functional levels due to oversimplifications which result from the application of highly
abstract and technology-independent fault models.
In this paper a novel behavioural level test generation algorithm is presented effectively
utilizing information on the circuit structure, which is extracted from the high level
synthesis process.
Experimental results show that the gate level fault coverage of the test sets generated
by the new algorithm is similar to those assured by the gate level test generation
algorithms
Fault simulation for structural testing of analogue integrated circuits
In this thesis the ANTICS analogue fault simulation software is described which provides a statistical approach to fault simulation for accurate analogue IC test evaluation. The traditional figure of fault coverage is replaced by the average probability of fault detection. This is later refined by considering the probability of fault occurrence to generate a more realistic, weighted test metric. Two techniques to reduce the fault simulation time are described, both of which show large reductions in simulation time with little loss of accuracy. The final section of the thesis presents an accurate comparison of three test techniques and an evaluation of dynamic supply current monitoring. An increase in fault detection for dynamic supply current monitoring is obtained by removing the DC component of the supply current prior to measurement
Automatic test pattern generation for asynchronous circuits
The testability of integrated circuits becomes worse with transistor dimensions reaching nanometer
scales. Testing, the process of ensuring that circuits are fabricated without defects, becomes
inevitably part of the design process; a technique called design for test (DFT). Asynchronous
circuits have a number of desirable properties making them suitable for the challenges posed
by modern technologies, but are severely limited by the unavailability of EDA tools for DFT
and automatic test-pattern generation (ATPG).
This thesis is motivated towards developing test generation methodologies for asynchronous
circuits. In total four methods were developed which are aimed at two different fault models:
stuck-at faults at the basic logic gate level and transistor-level faults. The methods were
evaluated using a set of benchmark circuits and compared favorably to previously published
work.
First, ABALLAST is a partial-scan DFT method adapting the well-known BALLAST technique
for asynchronous circuits where balanced structures are used to guide the selection of
the state-holding elements that will be scanned. The test inputs are automatically provided
by a novel test pattern generator, which uses time frame unrolling to deal with the remaining,
non-scanned sequential C-elements. The second method, called AGLOB, uses algorithms
from strongly-connected components in graph graph theory as a method for finding the optimal
position of breaking the loops in the asynchronous circuit and adding scan registers. The
corresponding ATPG method converts cyclic circuits into acyclic for which standard tools can
provide test patterns. These patterns are then automatically converted for use in the original
cyclic circuits. The third method, ASCP, employs a new cycle enumeration method to find the
loops present in a circuit. Enumerated cycles are then processed using an efficient set covering
heuristic to select the scan elements for the circuit to be tested.Applying these methods to
the benchmark circuits shows an improvement in fault coverage compared to previous work,
which, for some circuits, was substantial. As no single method consistently outperforms the
others in all benchmarks, they are all valuable as a designer’s suite of tools for testing. Moreover,
since they are all scan-based, they are compatible and thus can be simultaneously used in
different parts of a larger circuit.
In the final method, ATRANTE, the main motivation of developing ATPG is supplemented by
transistor level test generation. It is developed for asynchronous circuits designed using a State
Transition Graph (STG) as their specification. The transistor-level circuit faults are efficiently
mapped onto faults that modify the original STG. For each potential STG fault, the ATPG tool
provides a sequence of test vectors that expose the difference in behavior to the output ports.
The fault coverage obtained was 52-72 % higher than the coverage obtained using the gate
level tests. Overall, four different design for test (DFT) methods for automatic test pattern generation
(ATPG) for asynchronous circuits at both gate and transistor level were introduced in this thesis.
A circuit extraction method for representing the asynchronous circuits at a higher level of
abstraction was also implemented.
Developing new methods for the test generation of asynchronous circuits in this thesis facilitates
the test generation for asynchronous designs using the CAD tools available for testing the
synchronous designs. Lessons learned and the research questions raised due to this work will
impact the future work to probe the possibilities of developing robust CAD tools for testing the
future asynchronous designs
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