Fast physical models for Si LDMOS power transistor characterization

A new nonlinear, process-oriented, quasi-two-dimensional (Q2D) model is described for microwave laterally diffused MOS (LDMOS) power transistors. A set of one-dimensional energy transport equations are solved across a two-dimensional cross-section in a “current-driven” form. The model accounts for avalanche breakdown and gate conduction, and accurately predicts DC and microwave characteristics at execution speeds sufficiently fast for circuit simulation applications

When self-consistency makes a difference

Compound semiconductor power RF and microwave device modeling requires, in many cases, the use of selfconsistent electrothermal equivalent circuits. The slow thermal dynamics and the thermal nonlinearity should be accurately included in the model; otherwise, some response features subtly related to the detailed frequency behavior of the slow thermal dynamics would be inaccurately reproduced or completely distorted. In this contribution we show two examples, concerning current collapse in HBTs and modeling of IMPs in GaN HEMTs. Accurate thermal modeling is proved to be be made compatible with circuit-oriented CAD tools through a proper choice of system-level approximations; in the discussion we exploit a Wiener approach, but of course the strategy should be tailored to the specific problem under consideratio

RF Compact Modeling of High-voltage MOSFETs

The High-Voltage MOSFET is used in a wide variety of applications covering from power systems up to RF-IC. Compact models that describe the high-frequency behavior of the device are required to predict high-frequency operation and switching capabilities of these elements in HV state-of-the-art systems. In this paper, an RF model is presented and verified against extensive Y-parameter measurements, which were carried out on a long channel Lateral double-Diffusion MOS device. Assessment of the model with measurements confirms the validity of this approach

Chip- and System-Level Reliability on SiC-based Power Modules

The blocking voltage, switching frequency and temperature tolerance of power devices have been greatly improved due to the revolution of wide bandgap (WBG) materials, such as silicon carbide (SiC) and gallium nitride (GaN). Owing to the development of SiC-based power devices, the power rating, operating voltage, and power density of power modules have been significantly improved. However, the reliability of SiC-based power modules has not been fully explored yet. Thus, this dissertation focuses on the chip- and system-level reliability on SiC-based power modules. For chip-level reliability, this work focuses on on-chip SiC ESD protection devices for SiC-based integrated circuits (ICs). In order to develop SiC ESD protection devices, SiC-based Ohmic contact and ion implantation have been studied. Nickel/Titanium/Aluminum (Ni/Ti/Al) metal stacks were deposited on SiC substrates to form Ohmic contact. Circular transfer length method (CTLM) structures were fabricated to characterize contact resistivity. Ion implantation was designed and simulated by Sentraurus technology computer aided design (TCAD) software. Secondary-ion mass spectrometry (SIMS) results show a good match with the simulation results. In addition, SiC ESD protection devices, such as N-type metal-oxide-semiconductor (NMOS), laterally diffused metal-oxide-semiconductor (LDMOS), high-voltage silicon controlled rectifier (HV-SCR) and low-voltage silicon controlled rectifier (LV-SCR), have been designed. Transmission line pulse (TLP) and very fast TLP (VF-TLP) measurements were carried out to characterize their ESD performance. The proposed SiC-based HV-SCR shows the highest failure current on TLP measurement and can be used as an area-efficient ESD protection device. On the other hand, for system-level reliability, this dissertation focuses on the galvanic isolation of high-temperature SiC power modules. Low temperature co-fired ceramics (LTCC) based high-temperature optocouplers were designed and fabricated as galvanic isolators. The LTCC-based high-temperature optocouplers show promising driving capability and steady response speed from 25 ºC to 250 ºC. In order to verify the performance of the high-temperature optocouplers at the system level, LTCC-based gate drivers that utilize the high-temperature optocouplers as galvanic isolators were designed and integrated into a high-temperature SiC-based power module. Finally, the high-temperature power module with integrated LTCC-based gate drivers was characterized by DPTs from 25 ºC to 200 ºC. The power module shows reliable switching performance at elevated temperatures

Electrical characterization and modelling of lateral DMOS transistor:investigation of capacitances and hot-carrier impact

With the work reported in this manuscript we have essentially contributed to the electrical characterization and modelling of high voltage MOSFETs, more particularly DMOS architectures such as X-DMOS and L-DMOS able to sustain voltages ranging from 30V to 100V. The technology information and the investigated devices have been kindly provided by AMIS, Belgium (former Alcatel Microelectronics). In general, all the initial defined targets in term of the orientation of our work, as defined in the introduction chapter, have been maintained along the progress of the work. However, sometimes, based on the obtained results we have decided to pay more attention to some less explored topics such as the hot carrier impact of DMOS capacitances and the combined effect of stress and temperature, which initially were not among the planned activities. However, we believe that we have contributed to some of the planned targets. We experimentally validated the concept of intrinsic drain voltage; a modeling concept dedicated to the modeling of HV MOSFET and demonstrated its usefulness for the DC and AC modelling of HV devices. We proposed an original mathematical yet quasi-empirical formulation for the bias-dependent drift series resistance of DMOS transistor, which is very accurate for modelling all the regimes of operation of the high voltage device. We combined for the first time such a model with EKV low voltage MOSFET model developed at EPFL. We also have reported on models for the capacitances of high voltage devices at two levels: equivalent circuits for small signal operation based on VK-concept and large signal charge-based models. These models capture the main physical charge distribution in the device but they are less adapted for fast circuit simulation. In the field of device reliability, we have originally contributed to the investigation of hot carrier effects on DC and AC characteristics of DMOS transistors, with key emphasis on the degradation of transistor capacitances and the influence of the temperature. At our knowledge, our work reported in this chapter is among the first reports existing in this field. We have essentially shown that the monitoring of capacitance degradation if mandatory for a deep understanding of the degradation mechanisms and, in conjunction with DC parameter degradation, could offer correct insights for reliability issues. Even more, we have shown situations (by comparing two fundamental types of stresses) when the capacitance degradation method by HC is much more sensitive than DC parameter degradation method. Of course, some of the combined stress-temperature investigations were too complex to find very coherent explications for all the observed effects but our work stress out the interest and significance of such an approach for defining the SOA of high voltage devices, in general. Overall, our work can be considered as placed at the interface between electrical characterization and modelling of high voltage devices emerging from conventional low voltage CMOS technology, continuing the research tradition in the field established at the Electronics laboratory (LEG) of EPF Lausanne