A 300-800MHz Tunable Filter and Linearized LNA applied in a Low-Noise Harmonic-Rejection RF-Sampling Receiver

A multiband flexible RF-sampling receiver aimed at software-defined radio is presented. The wideband RF sampling function is enabled by a recently proposed discrete-time mixing downconverter. This work exploits a voltage-sensing LNA preceded by a tunable LC pre-filter with one external coil to demonstrate an RF-sampling receiver with low noise figure (NF) and high harmonic rejection (HR). The second-order LC filter provides voltage pre-gain and attenuates the source noise aliasing, and it also improves the HR ratio of the sampling downconverter. The LNA consists of a simple amplifier topology built from inverters and resistors to improve the third-order nonlinearity via an enhanced voltage mirror technique. The RF-sampling receiver employs 8 times oversampling covering 300 to 800 MHz in two RF sub-bands. The chip is realized in 65 nm CMOS and the measured gain across the band is between 22 and 28 dB, while achieving a NF between 0.8 to 4.3 dB. The IIP2 varies between +38 and +49 dBm and the IIP3 between -14 dBm and -9 dBm, and the third and fifth order HR ratios are more than 60 dB. The LNA and downconverter consumes 6 mW, and the clock generator takes 12 mW at 800 MHz RF.\ud \u

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

Broadband RF Front-End Design for Multi-Standard Receiver with High-Linearity and Low-Noise Techniques

Future wireless communication devices must support multiple standards and features on a single-chip. The trend towards software-defined radio requires flexible and efficient RF building blocks which justifies the adoption of broadband receiver front-ends in modern and future communication systems. The broadband receiver front-end significantly reduces cost, area, pins, and power, and can process several signal channels simultaneously. This research is mainly focused on the analysis and realization of the broadband receiver architecture and its various building blocks (LNA, Active Balun-LNA, Mixer, and trans-impedance amplifier) for multi-standard applications. In the design of the mobile DTV tuner, a direct-conversion receiver architecture is adopted achieving low power, low cost, and high dynamic-range for DVB-H standard. The tuner integrates a single-ended RF variable gain amplifier (RFVGA), a current-mode passive mixer, and a combination of continuous and discrete-time baseband filter with built-in anti-aliasing. The proposed RFVGA achieves high dynamic-range and gain-insensitive input impedance matching performance. The current-mode passive mixer achieves high gain, low noise, and high linearity with low power supplies. A wideband common-gate LNA is presented that overcomes the fundamental trade-off between power and noise match without compromising its stability. The proposed architecture can achieve the minimum noise figure over the previously reported feedback amplifiers in common-gate configuration. The proposed architecture achieves broadband impedance matching, low noise, large gain, enhanced linearity, and wide bandwidth concurrently by employing an efficient and reliable dual negative-feedback. For the wideband Inductorless Balun-LNA, active single-to-differential architecture has been proposed without using any passive inductor on-chip which occupies a lot of silicon area. The proposed Balun-LNA features lower power, wider bandwidth, and better gain and phase balance than previously reported architectures of the same kind. A surface acoustic wave (SAW)-less direct conversion receiver targeted for multistandard applications is proposed and fabricated with TSMC 0.13?m complementary metal-oxide-semiconductor (CMOS) technology. The target is to design a wideband SAW-less direct coversion receiver with a single low noise transconductor and current-mode passive mixer with trans-impedance amplifier utilizing feed-forward compensation. The innovations in the circuit and architecture improves the receiver dynamic range enabling highly linear direct-conversion CMOS front-end for a multi-standard receiver

Contribution à la conception d'un récepteur mobile failble coût et faible consommation dans la bande Ku pour le standard DVB-S

Cette thèse présente une étude de faisabilité d'un récepteur faible coût et faible consommation pour l'extension du standard DVS-S à la mobilité. L'objectif de ce projet est de proposer de solutions pour lever les verrous technologiques quant à la réalisation d'un tel système en technologie CMOS 65 nm. Ce manuscrit de thèse articulé autour de quatre chapitres décrit toutes les étapes depuis la définition des spécifications du réseau d'antennes et de la chaîne de réception jusqu'à la présentation de leurs performances, en passant par l'étude de leurs architectures et de la conception des différents blocs. Suite à l'étude au niveau système et au bilan de liaison, le démonstrateur envisagé est constitué d'un réseau d'antennes (huit sous-réseaux de huit antennes microruban) suivi de la mise en parallèle de huit chemins unitaires pour satisfaire les exigences (Gain, facteur de bruit, rapport signal-à-bruit...) de l'application visée. Ce travail a abouti à la démonstration de la faisabilité d'une architecture innovante. Par ailleurs, nous avons aussi démontré sa non-application pour le standard DVB-S en raison des limitations en bruit de la technologie CMOS. Cependant des pistes existent pour améliorer le rapport signal-à-bruit du démonstrateur, à savoir l'utilisation d'un LNA (Low Noise Amplifier) avec une technologie compétitive en bruit et/ou d'un traitement du signal après la démodulation en bande par un processeur analogique.This work focuses on the faisability of a low cost and low power receiver in order to extend the DVB-S standard to mobility. The objective of this project is to suggest solutions to overcome technological bottlenecks fot the realization of such a demonstrator with 65 nm CMOS technology. This report composed of four chapters, describes all steps from the specification definition to the performances of the antenna array and the receiver through the architecture study and the different blocks design. [...]BORDEAUX1-Bib.electronique (335229901) / SudocSudocFranceF

Digitally-Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative “iterative” harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and 3.5 dBm in-band IIP3 while the out-of-band IIP3 is + 16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply

Design of a phased array antenna for a DVB-T based passive bistatic radar

This thesis was initiated by the Norwegian Defence Research Establishment's military air surveillance project on passive radar systems. The main objective of the thesis is the design of a phased array antenna for a DVB-T based passive bistatic radar.\\Design specifications for this array has been derived based on the radar's required sectoral coverage available DVB-T transmitters in the vicinity of the Oslo fjord. An 11 element horizontal linear array with dual polarized elements was found suitable for the application, where the bandwidth of the array should at least cover 622 MHz to 726 MHz, corresponding to DVB-T channels 40-52.\\\noindent A crossed bowtie antenna was found suitable as an array element and modelling and simulations were done using CST Microwave Studio. The resulting simulated bandwidth was from 624 MHz to 748 MHz for the horizontally polarized elements and 600 MHz to 800 MHz for the vertically polarized elements with an input reflection coefficient below -10 dB. In terms of radiation patterns, the center element of the array showed a half-power beamwidth in the horizontal plane of $122^{\circ}$ and $130^{\circ}$ for the horizontally and vertically polarized elements respectively. In the vertical plane the corresponding beamwidths was $120^{\circ}$ and $88^{\circ}$. When the array was scanned, the grating-lobe free scan range was $\theta_s = \pm 50^{\circ}$ at the highest operating frequency of 750 MHz, where the active reflection coefficient at the center element was lower than -7dB throughout the whole band when scanned to this angle.\\\noindent In order to verify the results from simulations in CST, a 5-element prototype array was produced with the objective of comparing simulations on a 5-element array in CST with those obtained from the prototype. The hypothesis was that if the measured performance on the prototype array was within acceptable limits of the simulated results, then one can presume that a full 11 element array will perform according to the simulation results given above. The center element of the 5-element array showed almost identical performance in terms of radiation patterns for both horizontal and vertical polarization, however with a higher level of cross polarization. A shift in center frequency of 30 MHz was found in measurements and it was found that this most likely stems from the fact that the quarter-wave balun used in the prototype, was not included in CST simulations. Apart from this, the measurements on the prototype array suggests that the CST simulations on the full 11 element array are valid, thus serving as a motivational factor to build a full 11 element prototype and characterize it through measurements.\\\noindent To summarize, the designed phased array antenna could potentially used as a sensor for a DVB-T based passive bistatic radar, covering channels 40-55 with a horizontal plane scan range of $\pm 50^{\circ}$. For future work it is recommended that the issue related to the frequency shift is sorted out and another row of elements in the vertical plane should be considered to further reduce the beamwidth in this plane

BiCMOS high-performance ICs : from DC to mm-wave

Progress with silicon and silicon germanium (SiGe) based BiCMOS technologies over the past few years has been very impressive. This enables the implementation of traditional microwave and emerging mm-wave applications in silicon. The paper gives an overview of several high-performance ICs that have been implemented in a state-of-the-art BiCMOS technology (QUBiC4). Examples of high-performance ICs are described ranging from basic building blocks for mobile applications to highly integrated receiver and transmitter ICs for applications up to the mm-wave range

Direct sampling receivers for broadband communications

Today everything tends to be connected in the Internet of Things (IoT) universe, where a broad variety of communication standards and technologies are used for those connected devices. It is always a dream to design a Software-Defined Radio (SDR) supporting different standards solely based on the software configuration. As integrated-circuit (IC) manufacture and design advance, a partial of SDR can be realized. This thesis investigates one of the most important parts in a SDR: the analog design of a direct sampling (DS) receiver, which mainly consists of a broadband RF front end and a wideband ADC. Especially, a DS receiver shows a great flexibility and efficiency for the simultaneous reception of multiple channels comparing with the traditional parallelism of superheterodyne structure. The research contributions of this work include (1) demonstration and comparative analysis of two new architectures of broadband RFPGAs: voltage-mode: RFPGA-V and current-mode: RFPGA-I. RFPGA-V and RFPGA-I utilize an innovative interpolation method and current steering approach, respectively, to achieve a fine gain step of 0.25-dB over 40-dB gain range for several GHz frequency range. Besides, with innovative design, no off-chip inductor is needed for the both RFPGAs. (2) The design of a 5-GS/s 10b time-interleaved SAR. The ADC power efficiency is significantly improved by many design techniques: the low-energy CDAC switching scheme, optimized input common-mode voltage for comparator, optimal reduced radix-2 capacitor ratio for low-power reference buffers and higher conversion speed, etc. The lane-to-lane mismatches in a time-interleave ADC are minimized by using optimal floor plan and then are calibrated digitally. Three prototypes: the broadband RF front ends with RFPGA-V, the broadband RF front ends with RFPGA-I and a 5-GHz ADC, are fabricated to verify the proposed ideas in 28nm CMOS technology.Electrical and Computer Engineerin