Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Next generation analog-to-digital conversion using time-based encoding and digital synthesis techniques

The internet-of-things is a growing market segment which is based on an arrayof portable communication devices with high power efficiency. Advanced semiconductortechnology can easily improve their digital performance, but the samecannot be said for the analog blocks which are vital to their operation. Highperformance analog circuits continue to use conventional design techniques andarchitectures at the expense of power efficiency. Deeply scaled CMOS exaggeratesthis trade-off, opening the door for novel system techniques that take advantage ofthe digital nature of sub-micron transistors. This research focuses on two highlydigital ADCs which can mitigate the short channel effects of limited output swingand low intrinsic gain while also benefiting from process scaling.First, a multi-domain ADC is used to perform quantization on both voltageand time domain signals, relaxing the power-performance trade-off. This hybridapproach can lead to a high resolution, high efficiency data converter in scaledprocess. A prototype ADC was fabricated in 180nm CMOS, showing an SNDRof 73 dB, operating at 20 MHz sampling frequency, with a power consumption of1.28 mW.Next, an automated synthesis process is used to automatically generate a highspeed VCO-based quantizer from verilog code. Stochastic spatial averaging iscombined with a high speed open-loop noise-shaping quantizer to provide enhancedresolution in the presence of device mismatch. Simulation results of a prototypeADC in 180nm CMOS shows an SNDR of 49 dB, operating at 800 MHz samplingfrequency and 50 MHz signal bandwidth.Keywords: data converter, synthesis, verilog, ADC, SAR, TD

An FPGA-based 77 GHzs RADAR signal processing system for automotive collision avoidance

An FPGA implementable Verilog HDL based signal processing algorithm has been developed to detect the range and velocity of target vehicles using a MEMS based 77 GHz LFMCW long range automotive radar. The algorithm generates a tuning voltage to control a GaAs based VCO to produce a triangular chirp signal, controls the operation of MEMS components, and finally processes the IF signal to determine the range and veolicty of the detected targets. The Verilog HDL code has been developed targeting the Xilinx Virtex-5 SX50T FPGA. The developed algorithm enables the MEMS radar to detect 24 targets in an optimum timespan of 6.42 ms in the range of 0.4 to 200 m with a range resolution of 0.19 m and a maximum range error 0.25 m. A maximum relative velocity of ±300 km/h can be determined with a velocity resolution in HDL of 0.95 m/s and a maximum velocity error of 0.83 m/s with a sweep duration of 1 ms

Frequency domain laser velocimeter signal processor: A new signal processing scheme

A new scheme for processing signals from laser velocimeter systems is described. The technique utilizes the capabilities of advanced digital electronics to yield a smart instrument that is able to configure itself, based on the characteristics of the input signals, for optimum measurement accuracy. The signal processor is composed of a high-speed 2-bit transient recorder for signal capture and a combination of adaptive digital filters with energy and/or zero crossing detection signal processing. The system is designed to accept signals with frequencies up to 100 MHz with standard deviations up to 20 percent of the average signal frequency. Results from comparative simulation studies indicate measurement accuracies 2.5 times better than with a high-speed burst counter, from signals with as few as 150 photons per burst

Digital CMOS ISFET architectures and algorithmic methods for point-of-care diagnostics

Over the past decade, the surge of infectious diseases outbreaks across the globe is redefining how healthcare is provided and delivered to patients, with a clear trend towards distributed diagnosis at the Point-of-Care (PoC). In this context, Ion-Sensitive Field Effect Transistors (ISFETs) fabricated on standard CMOS technology have emerged as a promising solution to achieve a precise, deliverable and inexpensive platform that could be deployed worldwide to provide a rapid diagnosis of infectious diseases. This thesis presents advancements for the future of ISFET-based PoC diagnostic platforms, proposing and implementing a set of hardware and software methodologies to overcome its main challenges and enhance its sensing capabilities. The first part of this thesis focuses on novel hardware architectures that enable direct integration with computational capabilities while providing pixel programmability and adaptability required to overcome pressing challenges on ISFET-based PoC platforms. This section explores oscillator-based ISFET architectures, a set of sensing front-ends that encodes the chemical information on the duty cycle of a PWM signal. Two initial architectures are proposed and fabricated in AMS 0.35um, confirming multiple degrees of programmability and potential for multi-sensing. One of these architectures is optimised to create a dual-sensing pixel capable of sensing both temperature and chemical information on the same spatial point while modulating this information simultaneously on a single waveform. This dual-sensing capability, verified in silico using TSMC 0.18um process, is vital for DNA-based diagnosis where protocols such as LAMP or PCR require precise thermal control. The COVID-19 pandemic highlighted the need for a deliverable diagnosis that perform nucleic acid amplification tests at the PoC, requiring minimal footprint by integrating sensing and computational capabilities. In response to this challenge, a paradigm shift is proposed, advocating for integrating all elements of the portable diagnostic platform under a single piece of silicon, realising a ``Diagnosis-on-a-Chip". This approach is enabled by a novel Digital ISFET Pixel that integrates both ADC and memory with sensing elements on each pixel, enhancing its parallelism. Furthermore, this architecture removes the need for external instrumentation or memories and facilitates its integration with computational capabilities on-chip, such as the proposed ARM Cortex M3 system. These computational capabilities need to be complemented with software methods that enable sensing enhancement and new applications using ISFET arrays. The second part of this thesis is devoted to these methods. Leveraging the programmability capabilities available on oscillator-based architectures, various digital signal processing algorithms are implemented to overcome the most urgent ISFET non-idealities, such as trapped charge, drift and chemical noise. These methods enable fast trapped charge cancellation and enhanced dynamic range through real-time drift compensation, achieving over 36 hours of continuous monitoring without pixel saturation. Furthermore, the recent development of data-driven models and software methods open a wide range of opportunities for ISFET sensing and beyond. In the last section of this thesis, two examples of these opportunities are explored: the optimisation of image compression algorithms on chemical images generated by an ultra-high frame-rate ISFET array; and a proposed paradigm shift on surface Electromyography (sEMG) signals, moving from data-harvesting to information-focused sensing. These examples represent an initial step forward on a journey towards a new generation of miniaturised, precise and efficient sensors for PoC diagnostics.Open Acces

Energy-efficient data converter design in scaled CMOS technology

Data converters bridge the physical and digital worlds. They have been the crucial building blocks in modern electronic systems, and are expected to have a growing significance in the booming era of Internet-of-Things (IoT) and 5G communications. The applications raise energy-efficiency requirements for both low-speed and high-speed converters since they are widely deployed in wireless sensor nodes and portable devices. To explore the solutions, the author worked on three directions: 1) techniques to improve the efficiency of the low-speed converters including the comparator; 2) techniques to develop high-speed data converters including the reference stabilization; 3) new architecture to improve the efficiency of the capacitance-to-digital converter (CDC). In the first part, a power-efficient 10-bit SAR ADC featured with a gain-boosted dynamic comparator is presented. In energy-constrained applications, the converter is usually supplied with low supply voltage (e.g., 0.3 V-0.5 V), which reduces the comparator pre-amplifier (pre-amp) gain and results in higher noise. A novel comparator topology with a dynamic common-gate stage is proposed to increase the pre-amplification gain, thereby reducing noise and offset. Besides, statistical estimation and loading switching techniques are combined to further improve energy efficiency. A 40-nm CMOS prototype achieves a Walden FoM of 1.5 fJ/conversion-step while operating at 100-kS/s from a 0.5-V supply. To further improve the energy-efficiency of the comparator, a novel dynamic pre-amp is proposed. By using an inverter-based input pair powered by a floating reservoir capacitor, the pre-amp realizes both current reuse and dynamic bias, thereby significantly boosting g [subscript m] /I [subscript D] and reducing noise. Moreover, it greatly reduces the influence of the input common-mode (CM) voltage on the comparator performance, including noise, offset, and delay. A prototype comparator in 180-nm achieves 46-μV input-referred noise while consuming only 1 pJ per comparison under 1.2-V supply, which represents greater than 7 times energy efficiency boost compared to that of a Strong-Arm (SA) latch. The second part of this dissertation focuses on high-speed data converter techniques. A 10-bit high-speed two-stage loop-unrolled SAR ADC is presented. To reduce the SAR logic delay and power, each bit uses a dedicated comparator to store its output and generate an asynchronous clock for the next comparison. To suppress the comparator offset mismatch induced non-linearity, a shared pre-amp are employed in the second fine stage, which is implemented by a dynamic latch to avoid static power consumption. The prototype ADC in 40-nm CMOS achieves 55-dB peak SNDR at 200-MS/s sampling rate without any calibration. A key limiting factor for the SAR ADC to simultaneously achieve high speed and high resolution is the reference ripple settling problem caused by DAC switching. Unlike prior techniques that aim to minimize the reference ripple which requires large reference buffer power or on-chip decoupling capacitance area, this work proposes a new perspective: it provides an extra path for the full-sized reference ripple to couple to the comparator but with an opposite polarity, so that the effect of the reference ripple is canceled out, thus ensuring an accurate conversion result. The prototype 10-bit 120-MS/s SAR ADC is fabricated in 40-nm CMOS process and achieves an SNDR of 55 dB with only 3 pF reference decoupling capacitor. Finally, this dissertation also presents the design of an incremental time-domain two-step CDC. Unlike the classic two-step CDC, this work replaces the OTA-based active-RC integrator with a VCO-based integrator and performs time domain (TD) ΔΣ modulation. The VCO is mostly digital and consumes low power. Featuring the infinite DC gain in phase domain and intrinsic spatial phase quantization, this TDΔΣ enables a CDC design, achieving 85-dB SQNR by having only a 4-bit quantizer, a 1st-order loop and a low OSR of 15. The prototype fabricated in 40-nm CMOS achieves a resolution of 0.29 fF while dissipating only 0.083 nJ per conversion, which improves the energy efficiency by greater than 2 times comparing to that of state-of-the-art CDCsElectrical and Computer Engineerin

Hardware architectures for compact microwave and millimeter wave cameras

Millimeter wave SAR imaging has shown promise as an inspection tool for human skin for characterizing burns and skin cancers. However, the current state-of-the-art in microwave camera technology is not yet suited for developing a millimeter wave camera for human skin inspection. Consequently, the objective of this dissertation has been to build the necessary foundation of research to achieve such a millimeter wave camera. First, frequency uncertainty in signals generated by a practical microwave source, which is prone to drift in output frequency, was studied to determine its effect on SAR-generated images. A direct relationship was found between the level of image distortions caused by frequency uncertainty and the product of frequency uncertainty and distance between the imaging measurement grid and sample under test. The second investigation involved the development of a millimeter wave imaging system that forms the basic building block for a millimeter wave camera. The imaging system, composed of two system-on-chip transmitters and receivers and an antipodal Vivaldi-style antenna, operated in the 58-64 GHz frequency range and employed the ω-k SAR algorithm. Imaging tests on burnt pigskin showed its potential for imaging and characterizing flaws in skin. The final investigation involved the development of a new microwave imaging methodology, named Chaotic Excitation Synthetic Aperture Radar (CESAR), for designing microwave and millimeter wave cameras at a fraction of the size and hardware complexity of previous systems. CESAR is based on transmitting and receiving from all antennas in a planar array simultaneously. A small microwave camera operating in the 23-25 GHz frequency was designed and fabricated based on CESAR. Imaging results with the camera showed it was capable of basic feature detection for various applications --Abstract, page iv

Characterisation of MIMO radio propagation channels

Due to the incessant requirement for higher performance radio systems, wireless designers have been constantly seeking ways to improve spectrum efficiency, link reliability, service quality, and radio network coverage. During the past few years, space-time technology which employs multiple antennas along with suitable signalling schemes and receiver architectures has been seen as a powerful tool for the implementation of the aforementioned requirements. In particular, the concept of communications via Multiple-Input Multiple-Output (MIMO) links has emerged as one of the major contending ideas for next generation ad-hoc and cellular systems. This is inherently due to the capacities expected when multiple antennas are employed at both ends of the radio link. Such a mobile radio propagation channel constitutes a MIMO system. Multiple antenna technologies and in particular MIMO signalling are envisaged for a number of standards such as the next generation of Wireless Local Area Network (WLAN) technology known as 802.1 ln and the development of the Worldwide Interoperability for Microwave Access (WiMAX) project, such as the 802.16e. For the efficient design, performance evaluation and deployment of such multiple antenna (space-time) systems, it becomes increasingly important to understand the characteristics of the spatial radio channel. This criterion has led to the development of new sounding systems, which can measure both spatial and temporal channel information. In this thesis, a novel semi-sequential wideband MIMO sounder is presented, which is suitable for high-resolution radio channel measurements. The sounder produces a frequency modulated continuous wave (FMCW) or chirp signal with variable bandwidth, centre frequency and waveform repetition rate. It has programmable bandwidth up to 300 MHz and waveform repetition rates up to 300 Hz, and could be used to measure conventional high- resolution delay/Doppler information as well as spatial channel information such as Direction of Arrival (DOA) and Direction of Departure (DOD). Notably the knowledge of the angular information at the link ends could be used to properly design and develop systems such as smart antennas. This thesis examines the theory of multiple antenna propagation channels, the sounding architecture required for the measurement of such spatial channel information and the signal processing which is used to quantify and analyse such measurement data. Over 700 measurement files were collected corresponding to over 175,000 impulse responses with different sounder and antenna array configurations. These included measurements in the Universal Mobile Telecommunication Systems Frequency Division Duplex (UMTS-FDD) uplink band, the 2.25 GHz and 5.8 GHz bands allocated for studio broadcast MIMO video links, and the 2.4 GHz and 5.8 GHz ISM bands allocated for Wireless Local Area Network (WLAN) activity as well as for a wide range of future systems defined in the WiMAX project. The measurements were collected predominantly for indoor and some outdoor multiple antenna channels using sounding signals with 60 MHz, 96 MHz and 240 MHz bandwidth. A wide range of different MIMO antenna array configurations are examined in this thesis with varying space, time and frequency resolutions. Measurements can be generally subdivided into three main categories, namely measurements at different locations in the environment (static), measurements while moving at regular intervals step by step (spatial), and measurements while the receiver (or transmitter) is on the move (dynamic). High-scattering as well as time-varying MIMO channels are examined for different antenna array structures

Sea state estimation from inertial platform data for real-time ocean wave prediction

Ocean observation is vital in understanding how the oceans contribute toward climate change and other effects. This is one of many undertakings requiring a persistent presence in the oceans. These maritime activities are mainly carried out on large research vessels chartered for weeks at a time, which can be extremely costly. In addition, the data obtained when using these vessels are only short snapshots of the continual processes that occur. Recently, there has been a drive toward using Unmanned Surface Vehicles (USVs) and Unmanned Underwater Vehicles (UUVs), which can be deployed at a fraction of the cost, and provide greatly improved spatio-temporal data. The wave glider (WG) is one such autonomous marine robot used for persistent ocean research and other maritime activities, and forms the focus of this study. The WG is a low power USV/UUV hybrid that harnesses wave energy for propulsion, and has a small solar- and battery-powered thruster, and a rudder for steering. Due to effects of waves, currents, and other disturbances, the platform tends to veer off its desired path. Additionally, local sea state information is not taken into consideration while manoeuvring, hence energy extraction from ocean waves is not optimal. More sophisticated navigation algorithms operating on a per-wave strategy may improve accuracy along a specified path and maximise the energy uptake from the waves. To realise these improvements requires prediction of local wave behaviour. If one can predict what the wave field will be a short time in the future, then possible control action can be taken to efficiently navigate in the environment. Inertial measurements and wave modelling have been used to improve localisation of the WG platform directly, and predict the platform’s velocity. However there is limited work in the context of WG navigation. Hence the problem this dissertation aims to solve is the estimation and subsequent prediction of local wave behaviour. This work proposes a novel approach to estimate the sea state and hence predict short-term, local wave behaviour from inertial measurements on a slow-moving marine platform such as the WG. A Kalman filtering strategy consisting of a phase-locked loop and filter based sea state estimator is used to generate local height and angle of arrival estimates. This method offers an improvement over existing Fast Fourier Transform methods as it does not require long time series data to produce results, and enables the prediction of wave behaviour a short time into the future. The ideas are tested in simulation by generating wind waves using ocean wave models such as the Pierson Moskowitz model, and dynamic a dynamic model of the WG platform. In addition, a small scale lab experiment is carried out to verify the performance of the sea-state estimator developed. Preliminary results obtained indicate that relative wave height can be estimated on-board a marine platform, using only inertial sensors

Transceiver architectures and sub-mW fast frequency-hopping synthesizers for ultra-low power WSNs

Wireless sensor networks (WSN) have the potential to become the third wireless revolution after wireless voice networks in the 80s and wireless data networks in the late 90s. This revolution will finally connect together the physical world of the human and the virtual world of the electronic devices. Though in the recent years large progress in power consumption reduction has been made in the wireless arena in order to increase the battery life, this is still not enough to achieve a wide adoption of this technology. Indeed, while nowadays consumers are used to charge batteries in laptops, mobile phones and other high-tech products, this operation becomes infeasible when scaled up to large industrial, enterprise or home networks composed of thousands of wireless nodes. Wireless sensor networks come as a new way to connect electronic equipments reducing, in this way, the costs associated with the installation and maintenance of large wired networks. To accomplish this task, it is necessary to reduce the energy consumption of the wireless node to a point where energy harvesting becomes feasible and the node energy autonomy exceeds the life time of the wireless node itself. This thesis focuses on the radio design, which is the backbone of any wireless node. A common approach to radio design for WSNs is to start from a very simple radio (like an RFID) adding more functionalities up to the point in which the power budget is reached. In this way, the robustness of the wireless link is traded off for power reducing the range of applications that can draw benefit form a WSN. In this thesis, we propose a novel approach to the radio design for WSNs. We started from a proven architecture like Bluetooth, and progressively we removed all the functionalities that are not required for WSNs. The robustness of the wireless link is guaranteed by using a fast frequency hopping spread spectrum technique while the power budget is achieved by optimizing the radio architecture and the frequency hopping synthesizer Two different radio architectures and a novel fast frequency hopping synthesizer are proposed that cover the large space of applications for WSNs. The two architectures make use of the peculiarities of each scenario and, together with a novel fast frequency hopping synthesizer, proved that spread spectrum techniques can be used also in severely power constrained scenarios like WSNs. This solution opens a new window toward a radio design, which ultimately trades off flexibility, rather than robustness, for power consumption. In this way, we broadened the range of applications for WSNs to areas in which security and reliability of the communication link are mandatory