A VCO-based CMOS readout circuit for capacitive MEMS microphones

Microelectromechanical systems (MEMS) microphone sensors have significantly improved in the past years, while the readout electronic is mainly implemented using switched-capacitor technology. The development of new battery powered 'always-on” applications increasingly requires a low power consumption. In this paper, we show a new readout circuit approach which is based on a mostly digital Sigma Delta (SigmaDelta) analog-to-digital converter (ADC). The operating principle of the readout circuit consists of coupling the MEMS sensor to an impedance converter that modulates the frequency of a stacked-ring oscillator—a new voltage-controlled oscillator (VCO) circuit featuring a good trade-off between phase noise and power consumption. The frequency coded signal is then sampled and converted into a noise-shaped digital sequence by a time-to-digital converter (TDC). A time-efficient design methodology has been used to optimize the sensitivity of the oscillator combined with the phase noise induced by 1/𝑓 and thermal noise. The circuit has been prototyped in a 130 nm CMOS process and directly bonded to a standard MEMS microphone. The proposed VCO-based analog-to-digital converter (VCO-ADC) has been characterized electrically and acoustically. The peak signal-to-noise and distortion ratio (SNDR) obtained from measurements is 77.9 dB-A and the dynamic range (DR) is 100 dB-A. The current consumption is 750 muA at 1.8 V and the effective area is 0.12 mm2. This new readout circuit may represent an enabling advance for low-cost digital MEMS microphones.This research was funded by project TEC2017-82653-R of CICYT, Spain

Time-encoding analog-to-digital converters : bridging the analog gap to advanced digital CMOS? Part 2: architectures and circuits

The scaling of CMOS technology deep into the nanometer range has created challenges for the design of highperformance analog ICs: they remain large in area and power consumption in spite of process scaling. Analog circuits based on time encoding [1], [2], where the signal information is encoded in the waveform transitions instead of its amplitude, have been developed to overcome these issues. While part one of this overview article [3] presented the basic principles of time encoding, this follow-up article describes and compares the main time-encoding architectures for analog-to-digital converters (ADCs) and discusses the corresponding design challenges of the circuit blocks. The focus is on structures that avoid, as much as possible, the use of traditional analog blocks like operational amplifiers (opamps) or comparators but instead use digital circuitry, ring oscillators, flip-flops, counters, an so on. Our overview of the state of the art will show that these circuits can achieve excellent performance. The obvious benefit of this highly digital approach to realizing analog functionality is that the resulting circuits are small in area and more compatible with CMOS process scaling. The approach also allows for the easy integration of these analog functions in systems on chip operating at "digital" supply voltages as low as 1V and lower. A large part of the design process can also be embedded in a standard digital synthesis flow

Data acquisition techniques based on frequency-encoding applied to capacitive MEMS microphones

Mención Internacional en el título de doctorThis thesis focuses on the development of capacitive sensor readout circuits and data converters based on frequency-encoding. This research has been motivated by the needs of consumer electronics industry, which constantly demands more compact readout circuit for MEMS microphones and other sensors. Nowadays, data acquisition is mainly based on encoding signals in voltage or current domains, which is becoming more challenging in modern deep submicron CMOS technologies. Frequency-encoding is an emerging signal processing technique based on encoding signals in the frequency domain. The key advantage of this approach is that systems can be implemented using mostly-digital circuitry, which benefits from CMOS technology scaling. Frequencyencoding can be used to build phase referenced integrators, which can replace classical integrators (such as switched-capacitor based integrators) in the implementation of efficient analog-to-digital converters and sensor interfaces. The core of the phase referenced integrators studied in this thesis consists of the combination of different oscillator topologies with counters and highly-digital circuitry. This work addresses two related problems: the development of capacitive MEMS sensor readout circuits based on frequency-encoding, and the design and implementation of compact oscillator-based data converters for audio applications. In the first problem, the target is the integration of the MEMS sensor into an oscillator circuit, making the oscillation frequency dependent on the sensor capacitance. This way, the sound can be digitized by measuring the oscillation frequency, using digital circuitry. However, a MEMS microphone is a complex structure on which several parasitic effects can influence the operation of the oscillator. This work presents a feasibility analysis of the integration of a MEMS microphone into different oscillator topologies. The conclusion of this study is that the parasitics of the MEMS limit the performance of the microphone, making it inefficient. In contrast, replacing conventional ADCs with frequency-encoding based ADCs has proven a very efficient solution, which motivates the next problem. In the second problem, the focus is on the development of high-order oscillator-based Sigma-Delta modulators. Firstly, the equivalence between classical integrators and phase referenced integrators has been studied, followed by an overview of state-of-art oscillator-based converters. Then, a procedure to replace classical integrators by phase referenced integrators is presented, including a design example of a second-order oscillator based Sigma-Delta modulator. Subsequently, the main circuit impairments that limit the performance of this kind of implementations, such as phase noise, jitter or metastability, are described. This thesis also presents a methodology to evaluate the impact of phase noise and distortion in oscillator-based systems. The proposed method is based on periodic steady-state analysis, which allows the rapid estimation of the system dynamic range without resorting to transient simulations. In addition, a novel technique to analyze the impact of clock jitter in Sigma-Delta modulators is described. Two integrated circuits have been implemented in 0.13 μm CMOS technology to demonstrate the feasibility of high-order oscillator-based Sigma-Delta modulators. Both chips have been designed to feature secondorder noise shaping using only oscillators and digital circuitry. The first testchip shows a malfunction in the digital circuitry due to the complexity of the multi-bit counters. The second chip, implemented using single-bit counters for simplicity, shows second-order noise shaping and reaches 103 dB-A of dynamic range in the audio bandwidth, occupying only 0.04 mm2.Esta tesis se centra en el desarrollo de conversores de datos e interfaces para sensores capacitivos basados en codificación en frecuencia. Esta investigación está motivada por las necesidades de la industria, que constantemente demanda reducir el tamaño de este tipo de circuitos. Hoy en día, la adquisición de datos está basada principalmente en la codificación de señales en tensión o en corriente. Sin embargo, la implementación de este tipo de soluciones en tecnologías CMOS nanométricas presenta varias dificultades. La codificación de frecuencia es una técnica emergente en el procesado de señales basada en codificar señales en el dominio de la frecuencia. La principal ventaja de esta alternativa es que los sistemas pueden implementarse usando circuitos mayoritariamente digitales, los cuales se benefician de los avances de la tecnología CMOS. La codificación en frecuencia puede emplearse para construir integradores referidos a la fase, que pueden reemplazar a los integradores clásicos (como los basados en capacidades conmutadas) en la implementación de conversores analógico-digital e interfaces de sensores. Los integradores referidos a la fase estudiados en esta tesis consisten en la combinación de diferentes topologías de osciladores con contadores y circuitos principalmente digitales. Este trabajo aborda dos cuestiones relacionadas: el desarrollo de circuitos de lectura para sensores MEMS capacitivos basados en codificación temporal, y el diseño e implementación de conversores de datos compactos para aplicaciones de audio basados en osciladores. En el primer caso, el objetivo es la integración de un sensor MEMS en un oscilador, haciendo que la frecuencia de oscilación depe capacidad del sensor. De esta forma, el sonido puede ser digitalizado midiendo la frecuencia de oscilación, lo cual puede realizarse usando circuitos en su mayor parte digitales. Sin embargo, un micrófono MEMS es una estructura compleja en la que múltiples efectos parasíticos pueden alterar el correcto funcionamiento del oscilador. Este trabajo presenta un análisis de la viabilidad de integrar un micrófono MEMS en diferentes topologías de oscilador. La conclusión de este estudio es que los parasíticos del MEMS limitan el rendimiento del micrófono, causando que esta solución no sea eficiente. En cambio, la implementación de conversores analógico-digitales basados en codificación en frecuencia ha demostrado ser una alternativa muy eficiente, lo cual motiva el estudio del siguiente problema. La segunda cuestión está centrada en el desarrollo de moduladores Sigma-Delta de alto orden basados en osciladores. En primer lugar se ha estudiado la equivalencia entre los integradores clásicos y los integradores referidos a la fase, seguido de una descripción de los conversores basados en osciladores publicados en los últimos años. A continuación se presenta un procedimiento para reemplazar integradores clásicos por integradores referidos a la fase, incluyendo un ejemplo de diseño de un modulador Sigma-Delta de segundo orden basado en osciladores. Posteriormente se describen los principales problemas que limitan el rendimiento de este tipo de sistemas, como el ruido de fase, el jitter o la metaestabilidad. Esta tesis también presenta un nuevo método para evaluar el impacto del ruido de fase y de la distorsión en sistemas basados en osciladores. El método propuesto está basado en simulaciones PSS, las cuales permiten la rápida estimación del rango dinámico del sistema sin necesidad de recurrir a simulaciones temporales. Además, este trabajo describe una nueva técnica para analizar el impacto del jitter de reloj en moduladores Sigma-Delta. En esta tesis se han implementado dos circuitos integrados en tecnología CMOS de 0.13 μm, con el fin de demostrar la viabilidad de los moduladores Sigma-Delta de alto orden basados en osciladores. Ambos chips han sido diseñados para producir conformación espectral de ruido de segundo orden, usando únicamente osciladores y circuitos mayoritariamente digitales. El primer chip ha mostrado un error en el funcionamiento de los circuitos digitales debido a la complejidad de las estructuras multi-bit utilizadas. El segundo chip, implementado usando contadores de un solo bit con el fin de simplificar el sistema, consigue conformación espectral de ruido de segundo orden y alcanza 103 dB-A de rango dinámico en el ancho de banda del audio, ocupando solo 0.04 mm2.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Georges G.E. Gielen.- Secretario: José Manuel de la Rosa.- Vocal: Ana Rus

A programmable microsystem using system-on-chip for real-time biotelemetry

A telemetry microsystem, including multiple sensors, integrated instrumentation and a wireless interface has been implemented. We have employed a methodology akin to that for System-on-Chip microelectronics to design an integrated circuit instrument containing several "intellectual property" blocks that will enable convenient reuse of modules in future projects. The present system was optimized for low-power and included mixed-signal sensor circuits, a programmable digital system, a feedback clock control loop and RF circuits integrated on a 5 mm × 5 mm silicon chip using a 0.6 μm, 3.3 V CMOS process. Undesirable signal coupling between circuit components has been investigated and current injection into sensitive instrumentation nodes was minimized by careful floor-planning. The chip, the sensors, a magnetic induction-based transmitter and two silver oxide cells were packaged into a 36 mm × 12 mm capsule format. A base station was built in order to retrieve the data from the microsystem in real-time. The base station was designed to be adaptive and timing tolerant since the microsystem design was simplified to reduce power consumption and size. The telemetry system was found to have a packet error rate of 10<sup>-</sup><sup>3</sup> using an asynchronous simplex link. Trials in animal carcasses were carried out to show that the transmitter was as effective as a conventional RF device whilst consuming less power

Contribution to time domain readout circuits design for multi-standard sensing system for low voltage supply and high-resolution applications

Mención Internacional en el título de doctorThis research activity has the purpose of open new possibilities in the design of capacitance-to-digital converters (CDCs) by developing a solution based on time domain conversion. This can be applied to applications related with the Internet-of-Things (IoT). These applications are present in any electronic devices where sensing is needed. To be able to reduce the area of the whole system with the required performance, micro-electromechanical systems (MEMS) sensors are used in these applications. We propose a new family of sensor readout electronics to be integrated with MEMS sensors. Within the time domain converters, Dual Slope (DS) topology is very interesting to explore a new compromise between performances, area and power consumption. DS topology has been extensively used in instrumentation. The simplicity and robustness of the blocks inside classical DS converters it is the main advantage. However, they are not efficient for applications where higher bandwidth is required. To extend the bandwidth, DS converters have been introduced into ΔΣ loops. This topology has been named as integrating converters. They increase the bandwidth compare to classical DS architecture but at the expense of higher complexity. In this work we propose the use of a new family of DS converters that keep the advantages of the classical architecture and introduce noise shaping. This way the bandwidth is increased without extra blocks. The Self-Compensated noise-shaped DS converter (the name given to the new topology) keeps the signal transfer function (STF) and the noise transfer function (NTF) of Integrating converters. However, we introduce a new arrangement in the core of the converter to do noise shaping without extra circuitry. This way the simplicity of the architecture is preserved. We propose to use the Self-Compensated DS converter as a CDC for MEMS sensors. This work makes a study of the best possible integration of the two blocks to keep the signal integrity considering the electromechanical behavior of the sensor. The purpose of this front-end is to be connected to any kind of capacitive MEMS sensor. However, to prove the concepts developed in this thesis the architecture has been connected to a pressure MEMS sensor. An experimental prototype was implemented in 130-nm CMOS process using the architecture mentioned before. A peak SNR of 103.9 dB (equivalent to 1Pa) has been achieved within a time measurement of 20 ms. The final prototype has a power consumption of 220 μW with an effective area of 0.317 mm2. The designed architecture shows good performance having competitive numbers against high resolution topologies in amplitude domain.Esta actividad de investigación tiene el propósito de explorar nuevas posibilidades en el diseño de convertidores de capacitancia a digital (CDC) mediante el desarrollo de una solución basada en la conversión en el dominio del tiempo. Estos convertidores se pueden utilizar en aplicaciones relacionadas con el mercado del Internet-de-las-cosas (IoT). Hoy en día, estas aplicaciones están presentes en cualquier dispositivo electrónico donde se necesite sensar una magnitud. Para poder reducir el área de todo el sistema con el rendimiento requerido, se utilizan sensores de sistemas micro-electromecánicos (MEMS) en estas aplicaciones. Proponemos una nueva familia de electrónica de acondicionamiento para integrar con sensores MEMS. Dentro de los convertidores de dominio de tiempo, la topología del doble-rampa (DS) es muy interesante para explorar un nuevo compromiso entre rendimiento, área y consumo de energía. La topología de DS se ha usado ampliamente en instrumentación. La simplicidad y la solidez de los bloques dentro de los convertidores DS clásicos es la principal ventaja. Sin embargo, no son eficientes para aplicaciones donde se requiere mayor ancho de banda. Para ampliar el ancho de banda, los convertidores DS se han introducido en bucles ΔΣ. Esta topología ha sido nombrada como Integrating converters. Esta topología aumenta el ancho de banda en comparación con la arquitectura clásica de DS, pero a expensas de una mayor complejidad. En este trabajo, proponemos el uso de una nueva familia de convertidores DS que mantienen las ventajas de la arquitectura clásica e introducen la configuración del ruido. De esta forma, el ancho de banda aumenta sin bloques adicionales. El convertidor Self-Compensated noise-shaped DS (el nombre dado a la nueva topología) mantiene la función de transferencia de señal (STF) y la función de transferencia de ruido (NTF) de los Integrating converters. Sin embargo, presentamos una nueva topología en el núcleo del convertidor para conformar el ruido sin circuitos adicionales. De esta manera, se preserva la simplicidad de la arquitectura. Proponemos utilizar el Self-Compensated noise-shaped DS como un CDC para sensores MEMS. Este trabajo hace un estudio de la mejor integración posible de los dos bloques para mantener la integridad de la señal considerando el comportamiento electromecánico del sensor. El propósito de este circuito de acondicionamiento es conectarse a cualquier tipo de sensor MEMS capacitivo. Sin embargo, para demostrar los conceptos desarrollados en esta tesis, la arquitectura se ha conectado a un sensor MEMS de presión. Se ha implementado dos prototipos experimentales en un proceso CMOS de 130-nm utilizando la arquitectura mencionada anteriormente. Se ha logrado una relación señal-ruido máxima de 103.9 dB (equivalente a 1 Pa) con un tiempo de medida de 20 ms. El prototipo final tiene un consumo de energía de 220 μW con un área efectiva de 0.317 mm2. La arquitectura diseñada muestra un buen rendimiento comparable con las arquitecturas en el dominio de la amplitud que muestran resoluciones equivalentes.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Pieter Rombouts.- Secretario: Alberto Rodríguez Pérez.- Vocal: Dietmar Strãußnig

SNDR Limits of Oscillator-Based Sensor Readout Circuits.

This paper analyzes the influence of phase noise and distortion on the performance of oscillator-based sensor data acquisition systems. Circuit noise inherent to the oscillator circuit manifests as phase noise and limits the SNR. Moreover, oscillator nonlinearity generates distortion for large input signals. Phase noise analysis of oscillators is well known in the literature, but the relationship between phase noise and the SNR of an oscillator-based sensor is not straightforward. This paper proposes a model to estimate the influence of phase noise in the performance of an oscillator-based system by reflecting the phase noise to the oscillator input. The proposed model is based on periodic steady-state analysis tools to predict the SNR of the oscillator. The accuracy of this model has been validated by both simulation and experiment in a 130 nm CMOS prototype. We also propose a method to estimate the SNDR and the dynamic range of an oscillator-based readout circuit that improves by more than one order of magnitude the simulation time compared to standard time domain simulations. This speed up enables the optimization and verification of this kind of systems with iterative algorithms.This work has been funded by projects 610484 FP7-IAPP of the European Union and TEC2014-56879-R of CICYT, Spain. The authors would like to thank Roberto Nonis and Pedro Amaral from Infineon Technologies Austria AG for helpful discussions