32 research outputs found

    A CMOS 0.18μm 64×64 single photon image sensor with in-pixel 11b time-to-digital converter

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    The design and characterization of a CMOS 64×64 single-photon avalanche-diode (SPAD) array with in-pixel 11b time-to-digital converter (TDC) is presented. It is targeted for time-resolved imaging, in particular 3D imaging. The achieved pixel pitch is 64μm with a fill factor of 3.5%. The chip was fabricated in a 0.18μm standard CMOS technology and implements a double functionality: Time-of-Flight estimation and photon counting. The imager features a programmable time resolution for the array of TDCs from 625ps down to 145ps. The measured accuracy of the minimum time bin is lower than ±1LSB DNL and 1.7LSB INL. The TDC jitter over the full dynamic range is less than 1LSB. Die-to-die process variation and temperature are discarded by auto-calibration. Fast quenching/restore circuit on each pixel lowers the power consumption by limiting the avalanche currents. Time gatedoperation is possible as well.Office of Naval Research (USA) N000141410355Ministerio de Economía y Competitividad TEC2012-38921- C02, IPT- 2011-1625-430000, IPC- 20111009 CDTIJunta de Andalucía TIC 2012- 233

    Photon Counting and Direct ToF Camera Prototype Based on CMOS SPADs

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    This paper presents a camera prototype for 2D/3D image capture in low illumination conditions based on single-photon avalanche-diode (SPAD) image sensor for direct time-offlight (d-ToF). The imager is a 64×64 array with in-pixel TDC for high frame rate acquisition. Circuit design techniques are combined to ensure successful 3D image capturing under low sensitivity conditions and high level of uncorrelated noise such as dark count and background illumination. Among them an innovative time gated front-end for the SPAD detector, a reverse start-stop scheme and real-time image reconstruction at Ikfps are incorporated by the imager. To the best of our knowledge, this is the first ToF camera based on a SPAD sensor fabricated and proved for 3D image reconstruction in a standard CMOS process without any opto-flavor or high voltage option. It has a depth resolution of 1cm at an illumination power from less than 6nW/mm 2 down to 0.1nW/mm 2 .Office of Naval Research (USA) N000141410355Ministerio de Economía y Competitividad TEC2015-66878-C3- 1-RJunta de Andalucía P12-TIC 233

    On the calibration of a SPAD-based 3D imager with in-pixel TDC using a time-gated technique

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    The optical characterization of a CMOS 64×64 single-photon avalanche-diode (SPAD) array with in-pixel 11b time-to-digital converter (TDC) is presented. The overall full-width half-maximum (FWHM) of the detector ensemble SPAD plus TDC is 690ps. The sensor has been fabricated in a 0.18μm standard CMOS technology which features an average dark-count rate (DCR) of 42kHz at 1V excess voltage (V e ) and room temperature. The detector successfully uses its time-gating capability to mitigate this large amount of noise enabling the sensor for accurate time-of-flight (ToF) measurements. The effectiveness of the time-gating technique is experimentally demonstrated. According to measurements, a time window of 400ns is enough to ensure that the TDC is triggered by light rather than by spurious events.Office of Naval Research (USA) N000141410355Ministerio de Economía y Competitividad TEC2012-38921- C02, IPT- 2011-1625-430000, IPC- 20111009Junta de Andalucía TIC 2012- 233

    In-pixel Voltage-Controlled Ring-Oscillator for Phase Interpolation in ToF Image Sensors

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    The design and measurements of a CMOS pseudodifferential voltage-controlled ring-oscillator (VCRO) are presented. It is aimed to act as time interpolator for arrayable picosecond time-to-digital convertors (TDC). This design is incorporated into a 64×64 array of TDCs for time-of-flight (ToF) measurement. It has been fabricated in a 0.18μm standard CMOS technology. Small occupation area of 28×29μm2 and low average power consumption of 1.17mW at 850MHz are promising figures for this application field. Embedded phase alignment and instantaneous start-up time are required to minimize the offset of time interval measurements. The measured gain of the VCRO is of 477MHz/V with a frequency tuning range of 53%. Moreover it features a linearity of 99.4% over a wide range of control frequencies, namely from 400MHz to 850MHz. The phase noise is of 102dBc/Hz at 2MHz offset frequency from 850MHz.Junta de Andalucía, Consejería de Economía, Innovación, Ciencia y Empleo (CEICE) TIC 2012- 233

    Wide range 8ps incremental resolution time interval generator based on FPGA technology

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    Accurate generation of picosecond-resolution wide-range time intervals has become a necessity for the characterization of time-to-digital converters involved in time resolved imaging. This paper presents the design and measurement of a time interval generator based on FPGA technology. Although it can be employed in different automatic test setups, it has been designed to characterize an array of time-to-digital converters. It can work as periodic pulse/ frequency generator but also as a digital-to-time converter. The accuracy of periodic pulse generator is around 20ps RMS jitter over a time range of 600ps to 33ns. The incremental time resolution is 8ps and the repetition rate is up to 2MHz. The accuracy of the digital-to-time converter is less than 0.8LSB DNL and 2LSB INL, whilst the time resolution is 27ps. Full characterization of the module is reported including a comparison with state-of-the-art instruments in this field.Office of Naval Research (USA) N000141410355Ministerio de Economía y Competitividad TEC2012-38921- C02, IPT −2011-1625-430000, IPC- 20111009 CDTIJunta de Andalucía TIC 2012–233

    Active gating as a method to inhibit the crosstalk of Single Photon Avalanche Diodes in a shared well

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    This work presents low noise readout circuits for silicon pixel detectors based on Geiger mode avalanche photodiodes. Geiger mode avalanche photodiodes offer a high intrinsic gain as well as an excellent timing accuracy. In addition, they can be compatible with standard CMOS technologies. However, they suffer from a high intrinsic noise, which induces false counts indistinguishable from real events and represents an increase of the readout electronics area to store the false counts. We have developed new front-end electronic circuitry for Geiger mode avalanche photodiodes in a conventional 0.35 µm HV-CMOS technology based on a gated mode of operation that allows low noise operation. The performance of the pixel detector is triggered and synchronized with the particle beam thanks to the gated acquisition. The circuits allow low reverse bias overvoltage operation which also improves the noise figures. Experimental characterization of the fabricated front-end circuit is presented in this work

    Dynamic Range Extension of a SPAD Imager Using Non-Uniformity Correction Techniques

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    The extraordinary sensitivity of single-photon avalanche diodes (SPADs) makes these devices the ideal option for vision systems aimed at low-light applications. Nevertheless, there exist large dark count rate and photon detection probability non-uniformities, which reduce the dynamic range of the detector. As a result, the capability to create image contrast is severely damaged or even lost. This paper presents the implementation of a correction algorithm to compensate for the mentioned non-uniformities and thus extend the contrast of the generated images. To demonstrate its efficiency, the proposed technique is applied to real images obtained with a fabricated SPAD image sensor. An increase of more than 3 b of contrast is obtained.Peer ReviewedPostprint (author's final draft

    Enhancing the fill-factor of CMOS SPAD arrays using microlens integration

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    Arrays of single-photon avalanche diode (SPAD) detectors were fabricated, using a 0.35 μm CMOS technology process, for use in applications such as time-of-flight 3D ranging and microscopy. Each 150 x 150 μm pixel comprises a 30 μm active area diameter SPAD and its associated circuitry for counting, timing and quenching, resulting in a fill-factor of 3.14%. This paper reports how a higher effective fill-factor was achieved as a result of integrating microlens arrays on top of the 32 x 32 SPAD arrays. Diffractive and refractive microlens arrays were designed to concentrate the incoming light onto the active area of each pixel. A telecentric imaging system was used to measure the improvement factor (IF) resulting from microlens integration, whilst varying the f-number of incident light from f/2 to f/22 in one-stop increments across a spectral range of 500-900 nm. These measurements have demonstrated an increasing IF with fnumber, and a maximum of ~16 at the peak wavelength, showing a good agreement with theoretical values. An IF of 16 represents the highest value reported in the literature for microlenses integrated onto a SPAD detector array. The results from statistical analysis indicated the variation of detector efficiency was between 3-10% across the whole f-number range, demonstrating excellent uniformity across the detector plane with and without microlenses

    32 × 32 CMOS SPAD Imager for Gated Imaging, Photon Timing, and Photon Coincidence

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    We present the design and simulations of a single-photon sensitive imager based on single photon avalanche diodes (SPADs) with an innovative pixel architecture that includes four separate SPADs with independent active time-gating and quenching circuit, a shared time-to-digital converter (TDC) with 50-ps resolution, four independent photon counters, and multiple operation modes. The TDC is driven by smart arbitration logic, which preserves spatial information among the four detectors; furthermore, an alternative operation mode exploits photon-coincidence on multiple detectors to reduce the effect of high background levels, e.g., in light detection and ranging applications with strong ambient light. Key features are the ability to operate in simultaneous photon counting and timing modes for capturing 2-D and 3-D images of the scene in a single shot (frame), the option of a counting-only mode, reducing power consumption, and increasing achievable frame-rate when timing information is not needed, and the ability to individually shut down noisy detectors or to enable just some regions of interests
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