Formal mutation testing for Circus

International audienceContext: The demand from industry for more dependable and scalable test-development mechanisms has fostered the use of formal models to guide the generation of tests. Despite many advancements having been obtained with state-based models, such as Finite State Machines (FSMs) and Input/Output Transition Systems (IOTSs), more advanced formalisms are required to specify large, state-rich, concurrent systems. Circus, a state-rich process algebra combining Z, CSP and a refinement calculus, is suitable for this; however, deriving tests from such models is accordingly more challenging. Recently, a testing theory has been stated for Circus, allowing the verification of process refinement based on exhaustive test sets. Objective: We investigate fault-based testing for refinement from Circus specifications using mutation. We seek the benefits of such techniques in test-set quality assertion and fault-based test-case selection. We target results relevant not only for Circus, but to any process algebra for refinement that combines CSP with a data language. Method: We present a formal definition for fault-based test sets, extending the Circus testing theory, and an extensive study of mutation operators for Circus. Using these results, we propose an approach to generate tests to kill mutants. Finally, we explain how prototype tool support can be obtained with the implementation of a mutant generator, a translator from Circus to CSP, and a refinement checker for CSP, and with

Component based testing with IOCO

Component based testing concerns the integration of components which have already been tested separately. We show that, with certain restrictions, the ioco-test theory for conformance testing is suitable for component based testing, in the sense that the integration of fully conformant components is guaranteed to be correct. As a consequence, there is no need to re-test the integrated system for conformance. This result is also relevant for testing in context, since it implies that every failure of a system embedded in a test context can be reduced to a fault of the system itself

Weaving theory/practice for art as knowing in early childhood education

Early childhood education has a tradition of arts based pedagogy. Current emphasis on high stakes testing and test scores as evidence of learning, even for young children, has educators moving away from the arts as academic learning. This visual essay is an a/r/tographic inquiry with woven threads of theory/practice from this moving fault zone that support the arts as a way of knowing for the early years. Making and writing with woolen fibers and feathers form a mat as a surface that is thinking with encounters from teaching pre-service early childhood educators with art. The weaving is an opening to understanding that falling, fear, and knowing are temporary and can provoke what might be next for pre-service teachers and young children using art as learning

Synthesizing Adaptive Test Strategies from Temporal Logic Specifications

Constructing good test cases is difficult and time-consuming, especially if the system under test is still under development and its exact behavior is not yet fixed. We propose a new approach to compute test strategies for reactive systems from a given temporal logic specification using formal methods. The computed strategies are guaranteed to reveal certain simple faults in every realization of the specification and for every behavior of the uncontrollable part of the system's environment. The proposed approach supports different assumptions on occurrences of faults (ranging from a single transient fault to a persistent fault) and by default aims at unveiling the weakest one. Based on well-established hypotheses from fault-based testing, we argue that such tests are also sensitive for more complex bugs. Since the specification may not define the system behavior completely, we use reactive synthesis algorithms with partial information. The computed strategies are adaptive test strategies that react to behavior at runtime. We work out the underlying theory of adaptive test strategy synthesis and present experiments for a safety-critical component of a real-world satellite system. We demonstrate that our approach can be applied to industrial specifications and that the synthesized test strategies are capable of detecting bugs that are hard to detect with random testing

Supply Current Diagnosis in VLSI

This paper presents a technique based upon the power supply current signature (cd) which allows for the testing of mixed-signal systems, in situ. Through experiments with a microprocessor, the cd is shown to contain important information concerning the operational status of the system which may be easily extracted using approaches based on statistical signal detection theory. The fault-detection performance of these techniques is compared to that achieved through auto-regressive modeling of the cd

Fault tolerant control for nonlinear aircraft based on feedback linearization

The thesis concerns the fault tolerant flight control (FTFC) problem for nonlinear aircraft by making use of analytical redundancy. Considering initially fault-free flight, the feedback linearization theory plays an important role to provide a baseline control approach for de-coupling and stabilizing a non-linear statically unstable aircraft system. Then several reconfigurable control strategies are studied to provide further robust control performance:- A neural network (NN)-based adaption mechanism is used to develop reconfigurable FTFC performance through the combination of a concurrent updated learninglaw. - The combined feedback linearization and NN adaptor FTFC system is further improved through the use of a sliding mode control (SMC) strategy to enhance the convergence of the NN learning adaptor. - An approach to simultaneous estimation of both state and fault signals is incorporated within an active FTFC system.The faults acting independently on the three primary actuators of the nonlinear aircraft are compensated in the control system.The theoretical ideas developed in the thesis have been applied to the nonlinear Machan Unmanned Aerial Vehicle (UAV) system. The simulation results obtained from a tracking control system demonstrate the improved fault tolerant performance for all the presented control schemes, validated under various faults and disturbance scenarios.A Boeing 747 nonlinear benchmark model, developed within the framework of the GARTEUR FM-AG 16 project “fault tolerant flight control systems”,is used for the purpose of further simulation study and testing of the FTFC scheme developed by making the combined use of concurrent learning NN and SMC theory. The simulation results under the given fault scenario show a promising reconfiguration performance

A Discrete Event System approach to On-line Testing of digital circuits with measurement limitation

AbstractIn the present era of complex systems like avionics, industrial processes, electronic circuits, etc., on-the-fly or on-line fault detection is becoming necessary to provide uninterrupted services. Measurement limitation based fault detection schemes are applied to a wide range of systems because sensors cannot be deployed in all the locations from which measurements are required. This paper focuses towards On-Line Testing (OLT) of faults in digital electronic circuits under measurement limitation using the theory of discrete event systems. Most of the techniques presented in the literature on OLT of digital circuits have emphasized on keeping the scheme non-intrusive, low area overhead, high fault coverage, low detection latency etc. However, minimizing tap points (i.e., measurement limitation) of the circuit under test (CUT) by the on-line tester was not considered. Minimizing tap points reduces load on the CUT and this reduces the area overhead of the tester. However, reduction in tap points compromises fault coverage and detection latency. This work studies the effect of minimizing tap points on fault coverage, detection latency and area overhead. Results on ISCAS89 benchmark circuits illustrate that measurement limitation have minimal impact on fault coverage and detection latency but reduces the area overhead of the tester. Further, it was also found that for a given detection latency and fault coverage, area overhead of the proposed scheme is lower compared to other similar schemes reported in the literature