Astrometry and Photometry with Coronagraphs

We propose a solution to the problem of astrometric and photometric calibration of coronagraphic images with a simple optical device which, in theory, is easy to use. Our design uses the Fraunhofer approximation of Fourier optics. Placing a periodic grid of wires (we use a square grid) with known width and spacing in a pupil plane in front of the occulting coronagraphic focal plane mask produces fiducial images of the obscured star at known locations relative to the star. We also derive the intensity of these fiducial images in the coronagraphic image. These calibrator images can be used for precise relative astrometry, to establish companionship of other objects in the field of view through measurement of common proper motion or common parallax, to determine orbits, and to observe disk structure around the star quantitatively. The calibrator spots also have known brightness, selectable by the coronagraph designer, permitting accurate relative photometry in the coronagraphic image. This technique, which enables precision exoplanetary science, is relevant to future coronagraphic instruments, and is particularly useful for `extreme' adaptive optics and space-based coronagraphy.Comment: To appear in ApJ August 2006, 27 preprint style pages 4 figure

Desynchronization: Synthesis of asynchronous circuits from synchronous specifications

Asynchronous implementation techniques, which measure logic delays at run time and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst-case delays at design time, and constrain the clock cycle accordingly. De-synchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus permitting widespread adoption of asynchronicity, without requiring special design skills or tools. In this paper, we first of all study different protocols for de-synchronization and formally prove their correctness, using techniques originally developed for distributed deployment of synchronous language specifications. We also provide a taxonomy of existing protocols for asynchronous latch controllers, covering in particular the four-phase handshake protocols devised in the literature for micro-pipelines. We then propose a new controller which exhibits provably maximal concurrency, and analyze the performance of desynchronized circuits with respect to the original synchronous optimized implementation. We finally prove the feasibility and effectiveness of our approach, by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architectur

Advanced Timing and Synchronization Methodologies for Digital VLSI Integrated Circuits

This dissertation addresses timing and synchronization methodologies that are critical to the design, analysis and optimization of high-performance, integrated digital VLSI systems. As process sizes shrink and design complexities increase, achieving timing closure for digital VLSI circuits becomes a significant bottleneck in the integrated circuit design flow. Circuit designers are motivated to investigate and employ alternative methods to satisfy the timing and physical design performance targets. Such novel methods for the timing and synchronization of complex circuitry are developed in this dissertation and analyzed for performance and applicability.Mainstream integrated circuit design flow is normally tuned for zero clock skew, edge-triggered circuit design. Non-zero clock skew or multi-phase clock synchronization is seldom used because the lack of design automation tools increases the length and cost of the design cycle. For similar reasons, level-sensitive registers have not become an industry standard despite their superior size, speed and power consumption characteristics compared to conventional edge-triggered flip-flops.In this dissertation, novel design and analysis techniques that fully automate the design and analysis of non-zero clock skew circuits are presented. Clock skew scheduling of both edge-triggered and level-sensitive circuits are investigated in order to exploit maximum circuit performances. The effects of multi-phase clocking on non-zero clock skew, level-sensitive circuits are investigated leading to advanced synchronization methodologies. Improvements in the scalability of the computational timing analysis process with clock skew scheduling are explored through partitioning and parallelization.The integration of the proposed design and analysis methods to the physical design flow of integrated circuits synchronized with a next-generation clocking technology-resonant rotary clocking technology-is also presented. Based on the design and analysis methods presented in this dissertation, a computer-aided design tool for the design of rotary clock synchronized integrated circuits is developed

Photovoltaic potential in building façades

Tese de doutoramento, Sistemas Sustentáveis de Energia, Universidade de Lisboa, Faculdade de Ciências, 2018Consistent reductions in the costs of photovoltaic (PV) systems have prompted interest in applications with less-than-optimum inclinations and orientations. That is the case of building façades, with plenty of free area for the deployment of solar systems. Lower sun heights benefit vertical façades, whereas rooftops are favoured when the sun is near the zenith, therefore the PV potential in urban environments can increase twofold when the contribution from building façades is added to that of the rooftops. This complementarity between façades and rooftops is helpful for a better match between electricity demand and supply. This thesis focuses on: i) the modelling of façade PV potential; ii) the optimization of façade PV yields; and iii) underlining the overall role that building façades will play in future solar cities. Digital surface and solar radiation modelling methodologies were reviewed. Special focus is given to the 3D LiDAR-based model SOL and the CAD/plugin models DIVA and LadyBug. Model SOL was validated against measurements from the BIPV system in the façade of the Solar XXI building (Lisbon), and used to evaluate façade PV potential in different urban sites in Lisbon and Geneva. The plugins DIVA and LadyBug helped assessing the potential for PV glare from façade integrated photovoltaics in distinct urban blocks. Technologies for PV integration in façades were also reviewed. Alternative façade designs, including louvers, geometric forms and balconies, were explored and optimized for the maximization of annual solar irradiation using DIVA. Partial shading impacts on rooftops and façades were addressed through SOL simulations and the interconnections between PV modules were optimized using a custom Multi-Objective Genetic Algorithm. The contribution of PV façades to the solar potential of two dissimilar neighbourhoods in Lisbon was quantified using SOL, considering local electricity consumption. Cost-efficient rooftop/façade PV mixes are proposed based on combined payback times. Impacts of larger scale PV deployment on the spare capacity of power distribution transformers were studied through LadyBug and SolarAnalyst simulations. A new empirical solar factor was proposed to account for PV potential in future upgrade interventions. The combined effect of aggregating building demand, photovoltaic generation and storage on the self-consumption of PV and net load variance was analysed using irradiation results from DIVA, metered distribution transformer loads and custom optimization algorithms. SOL is shown to be an accurate LiDAR-based model (nMBE ranging from around 7% to 51%, nMAE from 20% to 58% and nRMSE from 29% to 81%), being the isotropic diffuse radiation algorithm its current main limitation. In addition, building surface material properties should be regarded when handling façades, for both irradiance simulation and PV glare evaluation. The latter appears to be negligible in comparison to glare from typical glaze/mirror skins used in high-rises. Irradiation levels in the more sunlit façades reach about 50-60% of the rooftop levels. Latitude biases the potential towards the vertical surfaces, which can be enhanced when the proportion of diffuse radiation is high. Façade PV potential can be increased in about 30% if horizontal folded louvers becomes a more common design and in another 6 to 24% if the interconnection of PV modules are optimized. In 2030, a mix of PV systems featuring around 40% façade and 60% rooftop occupation is shown to comprehend a combined financial payback time of 10 years, if conventional module efficiencies reach 20%. This will trigger large-scale PV deployment that might overwhelm current grid assets and lead to electricity grid instability. This challenge can be resolved if the placement of PV modules is optimized to increase self-sufficiency while keeping low net load variance. Aggregated storage within solar communities might help resolving the conflicting interests between prosumers and grid, although the former can achieve self-sufficiency levels above 50% with storage capacities as small as 0.25kWh/kWpv. Business models ought to adapt in order to create conditions for both parts to share the added value of peak power reduction due to optimized solar façades.Fundação para a Ciência e a Tecnologia (FCT), SFRH/BD/52363/201

Design, Fabrication, and Run-time Strategies for Hardware-Assisted Security

Today, electronic computing devices are critically involved in our daily lives, basic infrastructure, and national defense systems. With the growing number of threats against them, hardware-based security features offer the best chance for building secure and trustworthy cyber systems. In this dissertation, we investigate ways of making hardware-based security into a reality with primary focus on two areas: Hardware Trojan Detection and Physically Unclonable Functions (PUFs). Hardware Trojans are malicious modifications made to original IC designs or layouts that can jeopardize the integrity of hardware and software platforms. Since most modern systems critically depend on ICs, detection of hardware Trojans has garnered significant interest in academia, industry, as well as governmental agencies. The majority of existing detection schemes focus on test-time because of the limited hardware resources available at run-time. In this dissertation, we explore innovative run-time solutions that utilize on-chip thermal sensor measurements and fundamental estimation/detection theory to expose changes in IC power/thermal profile caused by Trojan activation. The proposed solutions are low overhead and also generalizable to many other sensing modalities and problem instances. Simulation results using state-of-the-art tools on publicly available Trojan benchmarks verify that our approaches can detect Trojans quickly and with few false positives. Physically Unclonable Functions (PUFs) are circuits that rely on IC fabrication variations to generate unique signatures for various security applications such as IC authentication, anti-counterfeiting, cryptographic key generation, and tamper resistance. While the existence of variations has been well exploited in PUF design, knowledge of exactly how variations come into existence has largely been ignored. Yet, for several decades the Design-for-Manufacturability (DFM) community has actually investigated the fundamental sources of these variations. Furthermore, since manufacturing variations are often harmful to IC yield, the existing DFM tools have been geared towards suppressing them (counter-intuitive for PUFs). In this dissertation, we make several improvements over current state-of-the-art work in PUFs. First, our approaches exploit existing DFM models to improve PUFs at physical layout and mask generation levels. Second, our proposed algorithms reverse the role of standard DFM tools and extend them towards improving PUF quality without harming non-PUF portions of the IC. Finally, since our approaches occur after design and before fabrication, they are applicable to all types of PUFs and have little overhead in terms of area, power, etc. The innovative and unconventional techniques presented in this dissertation should act as important building blocks for future work in cyber security

Advanced Applications of Rapid Prototyping Technology in Modern Engineering

Rapid prototyping (RP) technology has been widely known and appreciated due to its flexible and customized manufacturing capabilities. The widely studied RP techniques include stereolithography apparatus (SLA), selective laser sintering (SLS), three-dimensional printing (3DP), fused deposition modeling (FDM), 3D plotting, solid ground curing (SGC), multiphase jet solidification (MJS), laminated object manufacturing (LOM). Different techniques are associated with different materials and/or processing principles and thus are devoted to specific applications. RP technology has no longer been only for prototype building rather has been extended for real industrial manufacturing solutions. Today, the RP technology has contributed to almost all engineering areas that include mechanical, materials, industrial, aerospace, electrical and most recently biomedical engineering. This book aims to present the advanced development of RP technologies in various engineering areas as the solutions to the real world engineering problems

Index to 1984 NASA Tech Briefs, volume 9, numbers 1-4

Short announcements of new technology derived from the R&D activities of NASA are presented. These briefs emphasize information considered likely to be transferrable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. This index for 1984 Tech B Briefs contains abstracts and four indexes: subject, personal author, originating center, and Tech Brief Number. The following areas are covered: electronic components and circuits, electronic systems, physical sciences, materials, life sciences, mechanics, machinery, fabrication technology, and mathematics and information sciences