Ion-Beam-Induced Defects in CMOS Technology: Methods of Study

Ion implantation is a nonequilibrium doping technique, which introduces impurity atoms into a solid regardless of thermodynamic considerations. The formation of metastable alloys above the solubility limit, minimized contribution of lateral diffusion processes in device fabrication, and possibility to reach high concentrations of doping impurities can be considered as distinct advantages of ion implantation. Due to excellent controllability, uniformity, and the dose insensitive relative accuracy ion implantation has grown to be the principal doping technology used in the manufacturing of integrated circuits. Originally developed from particle accelerator technology, ion implanters operate in the energy range from tens eV to several MeV (corresponding to a few nms to several microns in depth range). Ion implantation introduces point defects in solids. Very minute concentrations of defects and impurities in semiconductors drastically alter their electrical and optical properties. This chapter presents methods of defect spectroscopy to study the defect origin and characterize the defect density of states in thin film and semiconductor interfaces. The methods considered are positron annihilation spectroscopy, electron spin resonance, and approaches for electrical characterization of semiconductor devices

Investigation and suppression of semiconductor–oxide related defect states : from surface science to device tests

Many present challenges in semiconductor technology are related to utilizing solid structures with atomic scale dimensions and materials with higher charge carrier mobility and/or other readily controllable properties. These include many surface-related problems because the ratio of surface parts of devices to the whole material volume increases all the time in practical device structures. One of the major problems has been oxidation of semiconductor surfaces during the manufacturing of devices. This PhD work deals with the surface and oxide interface properties of different III–V semiconductors induced by the oxidation, the study of which is imperative in realizing devices with desired characteristics. The general goal has been in finding answers to these problematic issues on atomic scale, and whether they can be resolved with simple parameter control of a thermal oxidation treatment. Much of the work leans on a previous novel finding of crystalline oxide phases on indium-containing III–V semiconductor (100) surfaces. Various aspects of applicability of such a structure in real semiconductor devices are considered in this work. Common denominator in all of the experiments and studies is that the initial investigations were carried out in very controlled environment in ultrahigh-vacuum: detailed basics and initial characterizations were carried out with high resolution and precision surface science methods. In particular, this work has resulted in novel crystalline oxide phases observed on GaSb(100) and InSb(111)B semiconductor surfaces. They have been extensively discussed from an applied point of view as well as their fundamental characteristics, relating to their already previously studied counterpart, InSb(100). Furthermore, beneficial passivating characteristics of a stabilizing crystalline InOx interfacial layer beneath an Al2O3 and reasons behind such behavior are demonstrated for InGaAs IR detector device structure. This thesis provides background of semiconductors, their surfaces, interfaces, and semiconductor technology as appropriate, research methods utilized, and briefly summarizes the findings of the work

Electrical overstress and electrostatic discharge failure in silicon MOS devices

This thesis presents an experimental and theoretical investigation of electrical failure in MOS structures, with a particular emphasis on short-pulse and ESD failure. It begins with an extensive survey of MOS technology, its failure mechanisms and protection schemes. A program of experimental research on MOS breakdown is then reported, the results of which are used to develop a model of breakdown across a wide spectrum of time scales. This model, in which bulk-oxide electron trapping/emission plays a major role, prohibits the direct use of causal theory over short time-scales, invalidating earlier theories on the subject. The work is extended to ESD stress of both polarities. Negative polarity ESD breakdownis found to be primarily oxide-voltage activated, with no significant dependence on temperature of luminosity. Positive polarity breakdown depends on the rate of surface inversion, dictated by the Si avalanche threshold and/or the generation speed of light-induced carriers. An analytical model, based upon the above theory is developed to predict ESD breakdown over a wide range of conditions. The thesis ends with an experimental and theoretical investigation of the effects of ESD breakdown on device and circuit performance. Breakdown sites are modelled as resistive paths in the oxide, and their distorting effects upon transistor performance are studied. The degradation of a damaged transistor under working stress is observed, giving a deeper insight into the latent hazards of ESD damage

Gate leakage variability in nano-CMOS transistors

Gate leakage variability in nano-scale CMOS devices is investigated through advanced modelling and simulations of planar, bulk-type MOSFETs. The motivation for the work stems from the two of the most challenging issues in front of the semiconductor industry - excessive leakage power, and device variability - both being brought about with the aggressive downscaling of device dimensions to the nanometer scale. The aim is to deliver a comprehensive tool for the assessment of gate leakage variability in realistic nano-scale CMOS transistors. We adopt a 3D drift-diffusion device simulation approach with density-gradient quantum corrections, as the most established framework for the study of device variability. The simulator is first extended to model the direct tunnelling of electrons through the gate dielectric, by means of an improved WKB approximation. A study of a 25 nm square gate n-type MOSFET demonstrates that combined effect of discrete random dopants and oxide thickness variation lead to starndard deviation of up to 50% (10%) of the mean gate leakage current in OFF(ON)-state of the transistor. There is also a 5 to 6 times increase of the magnitude of the gate current, compared to that simulated of a uniform device. A significant part of the research is dedicated to the analysis of the non-abrupt bandgap and permittivity transition at the Si/SiO2 interface. One dimensional simulation of a MOS inversion layer with a 1nm SiO2 insulator and realistic band-gap transition reveals a strong impact on subband quantisation (over 50mV reduction in the delta-valley splitting and over 20% redistribution of carriers from the delta-2 to the delta-4 valleys), and enhancement of capacitance (over 10%) and leakage (about 10 times), relative to simulations with an abrupt band-edge transition at the interface

A first-principles approach to closing the "10-100 eV gap" for charge-carrier thermalization in semiconductors

The present work is concerned with studying accurately the energy-loss processes that control the thermalization of hot electrons and holes that are generated by high-energy radiation in wurtzite GaN, using an ab initio approach. Current physical models of the nuclear/particle physics community cover thermalization in the high-energy range (kinetic energies exceeding ~100 eV), and the electronic-device community has studied extensively carrier transport in the low-energy range (below ~10 eV). However, the processes that control the energy losses and thermalization of electrons and holes in the intermediate energy range of about 10-100 eV (the "10-100 eV gap") are poorly known. The aim of this research is to close this gap, by utilizing density functional theory (DFT) to obtain the band structure and dielectric function of GaN for energies up to about 100 eV. We also calculate charge-carrier scattering rates for the major charge-carrier interactions (phonon scattering, impact ionization, and plasmon emission), using the DFT results and first-order perturbation theory. With this information, we study the thermalization of electrons starting at 100 eV using the Monte Carlo method to solve the semiclassical Boltzmann transport equation. Full thermalization of electrons and holes is complete within ~1 and 0.5 ps, respectively. Hot electrons dissipate about 90% of their initial kinetic energy to the electron-hole gas (90 eV) during the first ~0.1 fs, due to rapid plasmon emission and impact ionization at high energies. The remaining energy is lost more slowly as phonon emission dominates at lower energies (below ~10 eV). During the thermalization, hot electrons generate pairs with an average energy of ~8.9 eV/pair (11-12 pairs per hot electron). Additionally, during the thermalization, the maximum electron displacement from its original position is found to be on the order of 100 nm.Comment: 23 pages, 20 figures. This LaTex file uses RevTex4.2 from AP

Infrared receivers for low background astronomy: Incoherent detectors and coherent devices from one micrometer to one millimeter

The status of incoherent detectors and coherent receivers over the infrared wavelength range from one micrometer to one millimeter is described. General principles of infrared receivers are included, and photon detectors, bolometers, coherent receivers, and important supporting technologies are discussed, with emphasis on their suitability for low background astronomical applications. Broad recommendations are presented and specific opportunities are identified for development of improved devices

Gate oxide failure in MOS devices

The thesis presents an experimental and theoretical investigation of gate oxide breakdown in MOS networks, with a particular emphasis on constant voltage overstress failure. It begins with a literature search on gate oxide failure mechanisms, particularly time-dependent dielectric breakdown, in MOS devices. The experimental procedure is then reported for the study of gate oxide breakdown under constant voltage stress. The experiments were carried out on MOSFETs and MOS capacitor structures, recording the characteristics of the devices before and after the stress. The effects of gate oxide breakdown in one of the transistors in an nMOS inverter were investigated and several parameters were found to have changed. A mathematical model for oxide breakdown, based on physical mechanisms, is proposed. Both electron and hole trapping occurred during the constant voltage stress. Breakdown appears to take place when the trapped hole density reach a critical value. PSPICE simulations were performed for the MOSFETs, nMOS inverter and CMOS logic circuits. Two models of MOSFET with gate oxide short were validated. A good agreement between experiments and simulations was achieved

Interface study of high-k oxide and Ge for the future Ge based MOSFET device

Master'sMASTER OF SCIENC

Study of High-k Dielectrics and their Interfaces on Semiconductors for Device Applications

This thesis has focused on two emerging applications of high-k dielectrics in Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) and in Metal-InsulatorSemiconductor High Electron Mobility Transistors (MIS-HEMTs). The key aim has been to propose the best routes for passivation of semiconductor/high-k oxide interfaces by investigating the band alignments and interface properties of several oxides, such as Tm2O3, Ta2O5, ZrO2, Al2O3 and MgO, deposited on different semiconductors: Si, Ge, GaN, InGaAs and InGaSb. The electrical characterisation of fabricated MIS capacitor and (MIS)-HEMT devices have also been performed. Thulium silicate (TmSiO) has been identified as a promising candidate for integration as interfacial layer (IL) in HfO2/TiN MOSFETs. The physical properties of Tm2O3/IL/Si interface have been elucidated, where IL (TmSiO) has been formed using different post-deposition annealing (PDA) temperatures, from 550 to 750 °C. It has been found that the best-scaled stack (sub-nm IL) is formed at 550 °C PDA with a graded interface layer and a strong SiOx (Si 3+) component. A large valence band offset (VBO) of 2.8 eV and a large conduction band offset (CBO) of 1.9 eV have been derived for Tm2O3/Si by X-ray photoelectron spectroscopy (XPS) and variable angle spectroscopic ellipsometry. Further increase of device performance can be achieved by replacing Si with GaN for high frequency, high power and high-temperature operation. In this thesis, several GaN cleaning procedures have been considered: 30% NH4OH, 20% (NH4)2S, and 37% HCl. It has been found that the HCl treatment shows the lowest oxygen contamination and Garich surface, and hence has been used prior sputtering of Ta2O5, Al2O3, ZrO2 and MgO on GaN. The large VBOs of 1.1 eV and 1.2 eV have been derived for Al2O3 and MgO on GaN respectively, using XPS and Kraut’s method; the corresponding CBOs are 2.0 eV and 2.8 eV respectively, taking into account the band gaps of Al2O3 (6.5 eV) and MgO (7.4 eV) determined from XPS O 1s electron energy spectra. The lowest leakage currents were obtained for devices with Al2O3 and MgO, i.e. 5.3 ×10-6 A/cm2 and 3.2 ×10-6 A/cm2 at 1 V, respectively in agreement with high band offsets (> 1 eV). Furthermore, the effect of different surface treatments (HCl, O2 plasma and 1-Octadecanethiol (ODT)) prior to atomic layer deposition of Al2O3 on the GaN/AlGaN/GaN heterostructure has been investigated. The MIS-HEMTs fabricated using the low-cost ODT GaN surface treatment have been found to exhibit superior performance for power switching applications such as a low threshold voltage, VT of -12.3 V, hysteresis of 0.12 V, a small subthreshold voltage slope (SS) of 73 mV/dec, and a low density of interface states, Dit of 3.0 x10^12 cm-2eV-1. A comprehensive novel study of HfO2/InGaAs and Al2O3/InGaSb interfaces have also been conducted for use in III-V based MOSFETs. The addition of the plasma H2/TMA/H2 pre-cleaning has been found to be very effective in recovering etch damage on InGaAs, especially for (110) orientation, and led to the improvement of electrical characteristics. Furthermore, the combination of H2 plasma exposure and forming gas anneal yielded significantly improved metrics for Al2O3/InGaSb over the control HCltreated sample, with the 150 W plasma treatment giving both the highest capacitance and the lowest stretch out