This thesis presents an experimental and theoretical investigation of electrical failure
in MOS structures, with a particular emphasis on short-pulse and ESD failure. It begins with
an extensive survey of MOS technology, its failure mechanisms and protection schemes. A
program of experimental research on MOS breakdown is then reported, the results of which
are used to develop a model of breakdown across a wide spectrum of time scales. This
model, in which bulk-oxide electron trapping/emission plays a major role, prohibits the direct
use of causal theory over short time-scales, invalidating earlier theories on the subject.
The work is extended to ESD stress of both polarities. Negative polarity ESD
breakdownis found to be primarily oxide-voltage activated, with no significant dependence
on temperature of luminosity. Positive polarity breakdown depends on the rate of surface
inversion, dictated by the Si avalanche threshold and/or the generation speed of light-induced
carriers. An analytical model, based upon the above theory is developed to predict ESD
breakdown over a wide range of conditions.
The thesis ends with an experimental and theoretical investigation of the effects of
ESD breakdown on device and circuit performance. Breakdown sites are modelled as
resistive paths in the oxide, and their distorting effects upon transistor performance are
studied. The degradation of a damaged transistor under working stress is observed, giving
a deeper insight into the latent hazards of ESD damage
