Accurate simulations of the interplay between process and statistical variability for nanoscale FinFET-based SRAM cell stability

In this paper we illustrate how by using advanced atomistic TCAD tools the interplay between long-range process variation and short-range statistical variability in FinFETs can be accurately modelled and simulated for the purposes of Design-Technology Co-Optimization (DTCO). The proposed statistical simulation and compact modelling methodology is demonstrated via a comprehensive evaluation of the impact of FinFET variability on SRAM cell stability

Oxygen-insertion Technology for CMOS Performance Enhancement

Until 2003, the semiconductor industry followed Dennard scaling rules to improve complementary metal-oxide-semiconductor (CMOS) transistor performance. However, performance gains with further reductions in transistor gate length are limited by physical effects that do not scale commensurately with device dimensions: short-channel effects (SCE) due to gate-leakage-limited gate-oxide thickness scaling, channel mobility degradation due to enhanced vertical electric fields, increased parasitic resistances due to reductions in source/drain (S/D) contact area, and increased variability in transistor performance due to random dopant fluctuation (RDF) effects and gate work function variations (WFV). These emerging scaling issues, together with increased process complexity and cost, pose severe challenges to maintaining the exponential scaling of transistor dimensions. This dissertation discusses the benefits of oxygen-insertion (OI) technology, a CMOS performance booster, for overcoming these challenges. The benefit of OI technology to mitigate the increase in sheet resistance ($R_{sh}$) with decreasing junction depth ($X_J$) for ultra-shallow-junctions (USJs) relevant for deep-sub-micron planar CMOS transistors is assessed through the fabrication of $R_{sh}$ test structures, electrical characterization, and technology computer-aided design (TCAD) simulations. Experimental and secondary ion mass spectroscopy (SIMS) analyses indicate that OI technology can facilitate low-resistivity USJ formation by reducing $R_{sh}$ and $X_J$ due to retarded transient-enhanced-diffusion (TED) effects and enhanced dopant retention during post-implantation thermal annealing. It is also shown that a low-temperature-oxide (LTO) capping can increase $R_{sh}$ unfavorably due to lower dopant activation levels, which can be alleviated by OI technology. This dissertation extends the evaluation of OI technology to advanced FinFET technology, targeting 7/8-nm low power technology node. A bulk-Si FinFET design comprising a super-steep retrograde (SSR) fin channel doping profile achievable with OI technology is studied by three-dimensional (3-D) TCAD simulations. As compared with the conventional bulk-Si (control) FinFET design with a heavily-doped fin channel doping profile, SSR FinFETs can achieve higher $I_{on}/I_{off}$ ratios and reduce the sensitivity of device performance to variations due to the lightly doped fin channel. As compared with the SOI FinFET design, SSR FinFETs can achieve similarly low $V_{DD,min}$ for 6T-SRAM cell yield estimation. Both SSR and SOI design can provide for as much as 100 mV reduction in $V_{DD,min}$ compared with the control FinFET design. Overall, the SSR FinFET design that can be achieved with OI technology is demonstrated to be a cheaper alternative to the SOI FinFET technology for extending CMOS scaling beyond the 10-nm node. Finally, this dissertation investigates the benefits of OI technology for reducing the Schottky barrier height ($\Phi_{Bp}$) of a Pt/Ti/p-type Si metal-semiconductor (M/S) contact, which can be expected to help reduce the specific contact resistivity for a p-type silicon contact. Electrical measurements of back-to-back Schottky diodes, SIMS, and X-ray photoelectron spectroscopy (XPS) show that the reduction in $\Phi_{Bp}$ is associated with enhanced Ti 2p and Si 2p core energy level shifts. OI technology is shown to favor low-$\Phi_{Bp}$ Pt monosilicide formation during forming gas anneal (FGA) by suppressing the grain boundary diffusion of Pt atoms into the crystalline Si substrate

Cross-Layer Resiliency Modeling and Optimization: A Device to Circuit Approach

The never ending demand for higher performance and lower power consumption pushes the VLSI industry to further scale the technology down. However, further downscaling of technology at nano-scale leads to major challenges. Reduced reliability is one of them, arising from multiple sources e.g. runtime variations, process variation, and transient errors. The objective of this thesis is to tackle unreliability with a cross layer approach from device up to circuit level

Variability analysis of FinFET AC/RF performances through efficient physics-based simulations for the optimization of RF CMOS stages

A nearly insatiable appetite for the latest electronic device enables the electronic technology sector to maintain research momentum. The necessity for advancement with miniaturization of electronic devices is the need of the day. Aggressive downscaling of electronic devices face some fundamental limits and thus, buoy up the change in device geometry. MOSFETs have been the leading contender in the electronics industry for years, but the dire need for miniaturization is forcing MOSFET to be scaled to nano-scale and in sub-50 nm scale. Short channel effects (SCE) become dominant and adversely affect the performance of the MOSFET. So, the need for a novel structure was felt to suppress SCE to an acceptable level. Among the proposed devices, FinFETs (Fin Field Effect Transistors) were found to be most effective to counter-act SCE in electronic devices. Today, many industries are working on electronic circuits with FinFETs as their primary element.One of limitation which FinFET faces is device variability. The purpose of this work was to study the effect that different sources of parameter fluctuations have on the behavior and characteristics of FinFETs. With deep literature review, we have gained insight into key sources of variability. Different sources of variations, like random dopant fluctuation, line edge roughness, fin variations, workfunction variations, oxide thickness variation, and source/drain doping variations, were studied and their impact on the performance of the device was studied as well. The adverse effect of these variations fosters the great amount of research towards variability modeling. A proper modeling of these variations is required to address the device performance metric before the fabrication of any new generation of the device on the commercial scale. The conventional methods to address the characteristics of a device under variability are Monte-Carlo-like techniques. In Monte Carlo analysis, all process parameters can be varied individually or simultaneously in a more realistic approach. The Monte Carlo algorithm takes a random value within the range of each process parameter and performs circuit simulations repeatedly. The statistical characteristics are estimated from the responses. This technique is accurate but requires high computational resources and time. Thus, efforts are being put by different research groups to find alternative tools. If the variations are small, Green’s Function (GF) approach can be seen as a breakthrough methodology. One of the most open research fields regards "Variability of FinFET AC performances". One reason for the limited AC variability investigations is the lack of commercially available efficient simulation tools, especially those based on accurate physics-based analysis: in fact, the only way to perform AC variability analysis through commercial TCAD tools like Synopsys Sentaurus is through the so-called Monte Carlo approach, that when variations are deterministic, is more properly referred to as incremental analysis, i.e., repeated solutions of the device model with varying physical parameters. For each selected parameter, the model must be solved first in DC operating condition (working point, WP) and then linearized around the WP, hence increasing severely the simulation time. In this work, instead, we used GF approach, using our in-house Simulator "POLITO", to perform AC variability analysis, provided that variations are small, alleviating the requirement of double linearization and reducing the simulation time significantly with a slight trade-off in accuracy. Using this tool we have, for the first time addressed the dependency of FinFET AC parameters on the most relevant process variations, opening the way to its application to RF circuits. This work is ultimately dedicated to the successful implementation of RF stages in commercial applications by incorporating variability effects and controlling the degradation of AC parameters due to variability. We exploited the POLITO (in-house simulator) limited to 2D structures, but this work can be extended to the variability analysis of 3D FinFET structure. Also variability analysis of III-V Group structures can be addressed. There is also potentiality to carry out the sensitivity analysis for the other source of variations, e.g., thermal variations

Benchmarking the screen-grid field effect transistor (SGrFET) for digital applications

Continuous scaling of CMOS technology has now reached a state of evolution, therefore, novel device structures and new materials have been proposed for this purpose. The Screen- Grid field Effect Transistor is introduced as a as a novel device structure that takes advantage of several innovative aspects of the FinFET while introducing new geometrical feature to improve a FET device performance. The idea is to design a FET which is as small as possible without down-scaling issues, at the same time satisfying optimum device performance for both analogue and digital applications. The analogue operation of the SGrFET shows some promising results which make it interesting to continue the investigation on SGrFET for digital applications. The SGrFET addresses some of the concerns of scaled CMOS such as Drain Induce Barrier Lowering and sub-threshold slope, by offering the superior short channel control. In this work in order to evaluate SGrFET performance, the proposed device compared to the classical MOSFET and provides comprehensive benchmarking with finFETs. Both AC and DC simulations are presented using TaurusTM and MediciTM simulators which are commercially available via Synopsis. Initial investigation on the novel device with the single gate structure is carried out. The multi-geometrical characteristic of the proposed device is used to reduce parasitic capacitance and increase ION/IOFF ratio to improve device performance in terms of switching characteristic in different circuit structures. Using TaurusTM AC simulation, a small signal circuit is introduced for SGrFET and evaluated using both extracted small signal elements from TaurusTM and Y-parameter extraction. The SGrFET allows for the unique behavioural characteristics of an independent-gate device. Different configurations of double-gate device are introduced and benchmark against the finFET serving as a double gate device. Five different logic circuits, the complementary and N-inverter, the NOR, NAND and XOR, and controllable Current Mirror circuits are simulated with finFET and SGrFET and their performance compared. Some digital key merits are extracted for both finFET and SGrFET such as power dissipation, noise margin and switching speed to compare the devices under the investigation performance against each other. It is shown that using multi-geometrical feature in SGrFET together with its multi-gate operation can greatly decrease the number of device needed for the logic function without speed degradation and it can be used as a potential candidate in mix-circuit configuration as a multi-gate device. The initial fabrication steps of the novel device explained together with some in-house fabrication process using E-Beam lithography. The fabricated SGrFET is characterised via electrical measurements and used in a circuit configuration

Nano-scale TG-FinFET: Simulation and Analysis

Transistor has been designed and fabricated in the same way since its invention more than four decades ago enabling exponential shrinking in the channel length. However, hitting fundamental limits imposed the need for introducing disruptive technology to take over. FinFET - 3-D transistor - has been emerged as the first successor to MOSFET to continue the technology scaling roadmap. In this thesis, scaling of nano-meter FinFET has been investigated on both the device and circuit levels. The studies, primarily, consider FinFET in its tri-gate (TG) structure. On the device level, first, the main TCAD models used in simulating electron transport are benchmarked against the most accurate results on the semi-classical level using Monte Carlo techniques. Different models and modifications are investigated in a trial to extend one of the conventional models to the nano-scale simulations. Second, a numerical study for scaling TG-FinFET according to the most recent International Technology Roadmap of Semiconductors is carried out by means of quantum corrected 3-D Monte Carlo simulations in the ballistic and quasi-ballistic regimes, to assess its ultimate performance and scaling behavior for the next generations. Ballisticity ratio (BR) is extracted and discussed over different channel lengths. The electron velocity along the channel is analyzed showing the physical significance of the off-equilibrium transport with scaling the channel length. On the circuit level, first, the impact of FinFET scaling on basic circuit blocks is investigated based on the PTM models. 256-bit (6T) SRAM is evaluated for channel lengths of 20nm down to 7nm showing the scaling trends of basic performance metrics. In addition, the impact of VT variations on the delay, power, and stability is reported considering die-to-die variations. Second, we move to another peer-technology which is 28nm FD-SOI as a comparative study, keeping the SRAM cell as the test block, more advanced study is carried out considering the cell‘s stability and the evolution from dynamic to static metrics

Static random-access memory designs based on different FinFET at lower technology node (7nm)

Title from PDF of title page viewed January 15, 2020Thesis advisor: Masud H ChowdhuryVitaIncludes bibliographical references (page 50-57)Thesis (M.S.)--School of Computing and Engineering. University of Missouri--Kansas City, 2019The Static Random-Access Memory (SRAM) has a significant performance impact on current nanoelectronics systems. To improve SRAM efficiency, it is important to utilize emerging technologies to overcome short-channel effects (SCE) of conventional CMOS. FinFET devices are promising emerging devices that can be utilized to improve the performance of SRAM designs at lower technology nodes. In this thesis, I present detail analysis of SRAM cells using different types of FinFET devices at 7nm technology. From the analysis, it can be concluded that the performance of both 6T and 8T SRAM designs are improved. 6T SRAM achieves a 44.97% improvement in the read energy compared to 8T SRAM. However, 6T SRAM write energy degraded by 3.16% compared to 8T SRAM. Read stability and write ability of SRAM cells are determined using Static Noise Margin and N- curve methods. Moreover, Monte Carlo simulations are performed on the SRAM cells to evaluate process variations. Simulations were done in HSPICE using 7nm Asymmetrical Underlap FinFET technology. The quasiplanar FinFET structure gained considerable attention because of the ease of the fabrication process [1] – [4]. Scaling of technology have degraded the performance of CMOS designs because of the short channel effects (SCEs) [5], [6]. Therefore, there has been upsurge in demand for FinFET devices for emerging market segments including artificial intelligence and cloud computing (AI) [8], [9], Internet of Things (IoT) [10] – [13] and biomedical [17] –[18] which have their own exclusive style of design. In recent years, many Underlapped FinFET devices were proposed to have better control of the SCEs in the sub-nanometer technologies [3], [4], [19] – [33]. Underlap on either side of the gate increases effective channel length as seen by the charge carriers. Consequently, the source-to-drain tunneling probability is improved. Moreover, edge direct tunneling leakage components can be reduced by controlling the electric field at the gate-drain junction . There is a limitation on the extent of underlap on drain or source sides because the ION is lower for larger underlap. Additionally, FinFET based designs have major width quantization issue. The width of a FinFET device increases only in quanta of silicon fin height (HFIN) [4]. The width quantization issue becomes critical for ratioed designs like SRAMs, where proper sizing of the transistors is essential for fault-free operation. FinFETs based on Design/Technology Co-Optimization (DTCO_F) approach can overcome these issues [38]. DTCO_F follows special design rules, which provides the specifications for the standard SRAM cells with special spacing rules and low leakages. The performances of 6T SRAM designs implemented by different FinFET devices are compared for different pull-up, pull down and pass gate transistor (PU: PD:PG) ratios to identify the best FinFET device for high speed and low power SRAM applications. Underlapped FinFETs (UF) and Design/Technology Co-Optimized FinFETs (DTCO_F) are used for the design and analysis. It is observed that with the PU: PD:PG ratios of 1:1:1 and 1:5:2 for the UF-SRAMs the read energy has degraded by 3.31% and 48.72% compared to the DTCO_F-SRAMs, respectively. However, the read energy with 2:5:2 ratio has improved by 32.71% in the UF-SRAM compared to the DTCO_F-SRAMs. The write energy with 1:1:1 configuration has improved by 642.27% in the UF-SRAM compared to the DTCO_F-SRAM. On the other hand, the write energy with 1:5:2 and 2:5:2 configurations have degraded by 86.26% and 96% in the UF-SRAMs compared to the DTCO_F-SRAMs. The stability and reliability of different SRAMs are also evaluated for 500mV supply. From the analysis, it can be concluded that Asymmetrical Underlapped FinFET is better for high-speed applications and DTCO FinFET for low power applications.Introduction -- Next generation high performance device: FinFET -- FinFET based SRAM bitcell designs -- Benchmarking of UF-SRAMs and DTCO-F-SRAMS -- Collaborative project -- Internship experience at INTEL and Marvell Semiconductor -- Conclusion and future wor

Sub-10nm Transistors for Low Power Computing: Tunnel FETs and Negative Capacitance FETs

One of the major roadblocks in the continued scaling of standard CMOS technology is its alarmingly high leakage power consumption. Although circuit and system level methods can be employed to reduce power, the fundamental limit in the overall energy efficiency of a system is still rooted in the MOSFET operating principle: an injection of thermally distributed carriers, which does not allow subthreshold swing (SS) lower than 60mV/dec at room temperature. Recently, a new class of steep-slope devices like Tunnel FETs (TFETs) and Negative-Capacitance FETs (NCFETs) have garnered intense interest due to their ability to surpass the 60mV/dec limit on SS at room temperature. The focus of this research is on the simulation and design of TFETs and NCFETs for ultra-low power logic and memory applications. Using full band quantum mechanical model within the Non-Equilibrium Greens Function (NEGF) formalism, source-underlapping has been proposed as an effective technique to lower the SS in GaSb-InAs TFETs. Band-tail states, associated with heavy source doping, are shown to significantly degrade the SS in TFETs from their ideal value. To solve this problem, undoped source GaSb-InAs TFET in an i-i-n configuration is proposed. A detailed circuit-to-system level evaluation is performed to investigate the circuit level metrics of the proposed devices. To demonstrate their potential in a memory application, a 4T gain cell (GC) is proposed, which utilizes the low-leakage and enhanced drain capacitance of TFETs to realize a robust and long retention time GC embedded-DRAMs. The device/circuit/system level evaluation of proposed TFETs demonstrates their potential for low power digital applications. The second part of the thesis focuses on the design space exploration of hysteresis-free Negative Capacitance FETs (NCFETs). A cross-architecture analysis using HfZrOx ferroelectric (FE-HZO) integrated on bulk MOSFET, fully-depleted SOI-FETs, and sub-10nm FinFETs shows that FDSOI and FinFET configurations greatly benefit the NCFET performance due to their undoped body and improved gate-control which enables better capacitance matching with the ferroelectric. A low voltage NC-FinFET operating down to 0.25V is predicted using ultra-thin 3nm FE-HZO. Next, we propose one-transistor ferroelectric NOR type (Fe-NOR) non-volatile memory based on HfZrOx ferroelectric FETs (FeFETs). The enhanced drain-channel coupling in ultrashort channel FeFETs is utilized to dynamically modulate memory window of storage cells thereby resulting in simple erase-, program-and read-operations. The simulation analysis predicts sub-1V program/erase voltages in the proposed Fe-NOR memory array and therefore presents a significantly lower power alternative to conventional FeRAM and NOR flash memories