Broadband whole package FDTD simulation

Whole package analysis is becoming more and more important with the rapid expansion of high frequency electronics. The motivation of this thesis is to find and implement a new method for broadband whole package simulation. 3-dimension (3-D) whole package Finite Difference Time Domain (FDTD) simulation result was first reported in detail in this thesis. The FDTD method is a widely used full-wave time-domain simulation method used in the design and analysis for electromagnetic (EM) systems, such as antennas, wave propagating, and microwave circuits. Absorbing boundary condition (ABC), such as the perfect matched layer (PML) method, makes it possible to accurately analyze an EM structure involving complicated wave propagation in three-dimensional domain. Instead of running simulation at each frequency, time-domain solution gives complete frequencydomain response including coupling and dispersion effects. Chapter2 introduces the principle of FDTD and two important boundary condition methods. It also discusses the nonuniform grid numerical error, and gives the FDTD simulation and theoretical result. Flip chip package is one of the most important package types. Chapter 3 presents a wide band approach for characterizing multiple flip chips interconnects by the FDTD method. Detailed analysis for electrical performance for frequencies up to 40 GHz has been performed with variations of interconnect bumps (ball cross section and via cross section). Flip chips of three sizes are studied using FDTD method in detail. The relationship between reflection loss, via pad length, ball crosssection and via cross section is tabulated for future packaging design. Based on the simulation results, some design approaches are proposed for packaging structure operating at near 40 GHz. FDTD whole package simulation method is introduced at the beginning of Chapter 4, followed by discussion how to implement this method to specific packages. The packages used to host circuit in chapter 4 are microstrip line and fiip chip interconnects. The embedded circuits are ideal transmission line and an HP amplifier. Transient effects are observed when an amplifier is hosted in a package. Most of the simulations are processed under three-dimensional environment; twodimensional simulation is used for reference standard. All these results were first reported by the author of this thesis and his collaborators

Multi-level analysis of on-chip optical wireless links

Networks-on-chip are being regarded as a promising solution to meet the on-going requirement for higher and higher computation capacity. In view of future kilo-cores architectures, electrical wired connections are likely to become inefficient and alternative technologies are being widely investigated. Wireless communications on chip may be therefore leveraged to overcome the bottleneck of physical interconnections. This work deals with wireless networks-on-chip at optical frequencies, which can simplify the network layout and reduce the communication latency, easing the antenna on-chip integration process at the same time. On the other end, optical wireless communication on-chip can be limited by the heavy propagation losses and the possible cross-link interference. Assessment of the optical wireless network in terms of bit error probability and maximum communication range is here investigated through a multi-level approach. Manifold aspects, concurring to the final system performance, are simultaneously taken into account, like the antenna radiation properties, the data-rate of the core-to core communication, the geometrical and electromagnetic layout of the chip and the noise and interference level. Simulations results suggest that communication up to some hundreds of \u3bcm can be pursued provided that the antenna design and/or the target data-rate are carefully tailored to the actual layout of the chip

Direct and Inverse Computational Methods for Electromagnetic Scattering in Biological Diagnostics

Scattering theory has had a major roll in twentieth century mathematical physics. Mathematical modeling and algorithms of direct,- and inverse electromagnetic scattering formulation due to biological tissues are investigated. The algorithms are used for a model based illustration technique within the microwave range. A number of methods is given to solve the inverse electromagnetic scattering problem in which the nonlinear and ill-posed nature of the problem are acknowledged.Comment: 61 pages, 5 figure

Multi-level analysis of on-chip optical wireless links

Networks-on-chip are being regarded as a promising solution to meet the on-going requirement for higher and higher computation capacity. In view of future kilo-cores architectures, electrical wired connections are likely to become inefficient and alternative technologies are being widely investigated. Wireless communications on chip may be therefore leveraged to overcome the bottleneck of physical interconnections. This work deals with wireless networks-on-chip at optical frequencies, which can simplify the network layout and reduce the communication latency, easing the antenna on-chip integration process at the same time. On the other end, optical wireless communication on-chip can be limited by the heavy propagation losses and the possible cross-link interference. Assessment of the optical wireless network in terms of bit error probability and maximum communication range is here investigated through a multi-level approach. Manifold aspects, concurring to the final system performance, are simultaneously taken into account, like the antenna radiation properties, the data-rate of the core-to core communication, the geometrical and electromagnetic layout of the chip and the noise and interference level. Simulations results suggest that communication up to some hundreds of μm can be pursued provided that the antenna design and/or the target data-rate are carefully tailored to the actual layout of the chip

Simulation for Reliability, Hardware Security, and Ising Computing in VLSI Chip Design

The continued scaling of VLSI circuits has provided a wealth of opportunities andchallenges to the VLSI circuit design area. Both these challenges and opportunities, however,require new simulation tools that can enable their solution or exploitation as classicalmethods typically dealt with problem domains with smaller scales or less complexity. Inthis dissertation, simulation methods are presented to address the emerging VLSI designtopics of Electromigration induced aging and Ising computing and are then applied to theapplication areas of hardware security and graph partitioning respectively.The Electromigration aging effect in VLSI circuits is a long-term reliability issueaffecting current carrying metal wires leading to IR drop degradation. Typically, simpleanalytical equations can determine a wire’s effective age or if it will be affected by the EMaging effect at all. However, these classical methods are overly conservative and can lead toover design or unnecessary design iterations. Furthermore, it is expected that the EM agingeffect will become more severe in future Integrated Cirucits (ICs) due to increasing currentdensities and the prevalance of polycrystaline copper atom structures seen at small wiredimensions. For this reason, more comprehensive simulation techniques that can efficientlysimulate the EM effect with less conservative results can help mitigate overdesign andincrease design margins while reducing design iterations.The area of Hardware Security is becoming increasingly important as the chipsupply chain becomes more globalized and the integrity of chips becomes more diffiuclt toverify. Utilizing the accurate simulation techniques for EM, we can utilize this reliabilityeffect to demonstrate how a reliability based attack could be perpatrated. Furthermore, wecan utilize this aging effect as a defense mechanism to help us validate the integrity of anIC and detect counterfeit chips in the component supply chain market.Ising computing is an emerging method of solving combinatorial optimization problemsby simulating the interactions of so-called spin glasses and their interactions. Borrowingconcepts from quantum computing, this methods mimics the quantum interaction betweenspin glasses in such a way that finding a ground state of these spin glass models leadsto the solution of a particular problem. In this dissertation, effective methods of simulatingthe spin glass interactions using General Purpose Graphics Processing Units (GPGPUs)and finding their ground state are developed.In addition to the GPU based Ising model simulations, important combinatorialproblems can be mapped to the Ising model. In this dissertation the Ising solver is appliedto graph partitioning which can be utilized in VLSI design and many other domains as well.Specifically, solvers for the maxcut problem and the balanced min-cut partitioning problemare developed

Physics-Based Electromigration Modeling and Analysis and Optimization

Long-term reliability is a major concern in modern VLSI design. Literature has shown that reliability gets worse as technology advances. It is expected that the future VLSI systems would have shorter reliability-induced lifetime comparing with previous generations. Being one of the most serious reliability effects, electromigration (EM) is a physical phenomenon of the migration of metal atoms due to the momentum exchange between atoms and the conducting electrons. It can cause wire resistance change or open circuit and result in functional failure of the circuit. Power-ground networks are the most vulnerable part to EM effect among all the interconnect wires since the current flow on this part is the largest on the chip. With new generation oftechnology node and aggressive design strategies, more accurate and efficient EM models are required. However, traditional EM approaches are very conservative and cannot meet current aggressive design strategies. Besides circuit level, EM also need to be thoroughly studied in system level due to limited power and temperature budgets among cores on chip. This research focuses on developing physical level EM model for VLSI circuits and system level EM optimization for multi-core systems in order to overcome the aforementioned problems. Specifically, for physical level, we develop two EM immortality check methods and a power grid EM check method. Firstly, a voltage based EM immortality analysis has been developed. Immortality condition in nucleation phase can be determined fast and accurately for multi-segment interconnect wires. Secondly, a saturation volume based incubation phase immortality check method has been proposed. This method can further reduce the redundancy in VLSI circuit design by immortality check in multiphase. Furthermore, both immortality check methods are integrated into a new power grid EM check methodology (EMspice) as filter for EM analysis. These filters can accelerate the simulation by filtering out immortal trees so that we only need to do simulation on fewer trees that are mortal. Coupled EM simulation considering both hydrostatic stress and electronic current/voltage in the power grid network will be applied to these mortal trees. This tool can work seamlessly with commercial synthesis flow. Besides physical level reliability models, system level reliability optimization is also discussed in this research. A deep reinforcement learning based EM optimization has been proposed for multi-core system. Both long term reliability effect (hard error) and transient soft error are considered. Energy can be optimized with all the reliability and other constraints fast and accurately compared to existing reliability management techniques. Last but not least, a scheduling based reliability optimization method for multi-core systems has been proposed. NBTI, HCI and EM are considered jointly. Lifetime of the system can be improved significantly compared to traditional methods which mainly focus on utilization

Refueling: Preventing wire degradation due to electromigration

Electromigration is a major source of wire and via failure. Refueling undoes EM for bidirectional wires and power/ground grids-some of a chip's most vulnerable wires. Refueling exploits EM's self-healing effect by balancing the amount of current flowing in both directions of a wire. It can significantly extend a wire's lifetime while reducing the chip area devoted to wires.Peer ReviewedPostprint (published version

Effective data parallel computing on multicore processors

The rise of chip multiprocessing or the integration of multiple general purpose processing cores on a single chip (multicores), has impacted all computing platforms including high performance, servers, desktops, mobile, and embedded processors. Programmers can no longer expect continued increases in software performance without developing parallel, memory hierarchy friendly software that can effectively exploit the chip level multiprocessing paradigm of multicores. The goal of this dissertation is to demonstrate a design process for data parallel problems that starts with a sequential algorithm and ends with a high performance implementation on a multicore platform. Our design process combines theoretical algorithm analysis with practical optimization techniques. Our target multicores are quad-core processors from Intel and the eight-SPE IBM Cell B.E. Target applications include Matrix Multiplications (MM), Finite Difference Time Domain (FDTD), LU Decomposition (LUD), and Power Flow Solver based on Gauss-Seidel (PFS-GS) algorithms. These applications are popular computation methods in science and engineering problems and are characterized by unit-stride (MM, LUD, and PFS-GS) or 2-point stencil (FDTD) memory access pattern. The main contributions of this dissertation include a cache- and space-efficient algorithm model, integrated data pre-fetching and caching strategies, and in-core optimization techniques. Our multicore efficient implementations of the above described applications outperform nai¨ve parallel implementations by at least 2x and scales well with problem size and with the number of processing cores

STUDY ON-CHIP METAL-INSULATOR-SEMICONDUCTOR-METAL INTERCONNECTS WITH THE ALTERNATING-DIRECTION-IMPLICIT FINITE-DIFFERENCE TIME-DOMAIN METHOD

The Alternating-Direction-Implicit Finite-Difference Time-Domain method is used to analyze the on-chip Metal-Insulator-Semiconductor-Metal interconnects by solving Maxwell's equations in time domain. This method is efficient in solving problems with fine geometries much smaller than the shortest wavelength of interest. The iteration algorithm is evaluated thoroughly with respects to stability, numerical dispersion, grid size, time-step size etc.. The dielectric quasi-TEM mode, the slow wave mode, and the skin-effect mode of the MISM structure are all analyzed. We find that semiconductors can readily operate from the slow wave mode, to the transition region, to the skin effect mode in state of art technology. This thesis shows that the silicon substrate losses and the metal line losses can be modeled with high resolution. Signal dispersion and attenuation over a wide range of doping densities and operating frequencies is discussed. Accurate prediction of interconnect losses is critical for high-frequency design with highly constrained timing requirements