A State Assignment Procedure For Asynchronous Sequential Circuits

This paper presents a new procedure for constructing nonuniversal shared-row internal state assignments for asynchronous sequential circuits. The method consists basically of establishing an initial code with the minimum number of variables required to dis. © 1971, IEEE. All rights reserved

Pulse mode VLSI asynchronous circuits

A new basic VLSI circuit element is presented that can be used to realize pulse mode asynchronous sequential circuits. A synthesis procedure is developed along with an unconventional state assignment procedure. Level input asynchronous sequential circuits can be realized by converting a regular flow table into a differential mode flow table, thereby allowing the new synthesis technique to be general. The new circuits tolerate 1-1 crossovers. This circuit also provides a means for state sequence detection and real time fault detection

Synthesis heuristics for large asynchronous sequential circuits

Many well-known synthesis procedures for asynchronous sequential circuits produce minimal or near-minimal results, but are practical only for very small problems. These algorithms become unwieldy when applied to large circuits with, for example, three or more input variables and twenty or more internal states. New heuristic procedures are described which permit the synthesis of very large machines. Although the resulting designs are generally not minimal, the heuristics are able to produce near-minimal solutions orders of magnitude more rapidly than the minimal algorithms. A method for specifying sequential circuit behavior is presented. Input-output sequences define submachines or modules. When properly interconnected, these modules form the required sequential circuit. It is shown that the waveform and interconnection specifications may easily be translated into flow table form. A large flow table simplification heuristic is developed. The algorithm may be applied to tables having hundreds of rows, and handles both normal and non-normal mode circuit specifications. Nonstandard state assignment procedures for normal, fundamental mode asynchronous sequential circuits are examined. An algorithm for rapidly generating large flow table internal state assignments is proposed. The algorithms described have been programmed in PL/1 and incorporated into an automated design system for asynchronous circuits; the system also includes minimum and near-minimum variable state assignment generators, a code evaluation routine, a design equation generator, and two Boolean equation simplification procedures. Large sequential circuits designed using the system illustrate the utility of the heuristic procedures --Abstract, pages ii-iii

State assignments for non-normal asynchronous sequential circuits

There is a lack of procedures that can be used to find good internal state assignments for asynchronous sequential circuits operating in the non-normal mode. Presented here, are two generalized state assignments, which are functions only of the number of rows in a flow table. The suggested bounds for the generalized state assignments are m + [log₂m] and m + [m/2] internal state variables for a 2m-row flow table, where [ ] means next lowest integer . Both generalized state assignments produce group (linear) codes. The algorithms for generating these internal state assignments are easy and straight-forward to implement. It is shown that each of these state assignments satisfactorily encode certain classes of flow tables. Even though a general proof has not been found to show that these assignments were standard, worst-case situations have been constructed, and it has never been necessary to increase the suggested bounds. An internal state assignment procedure for obtaining non-standard or non-generalized state assignments is also presented. The internal state assignments, using the proposed method, are obtained in a systematic manner; and generally require fewer internal state variables than other procedures presently available --Abstract, page ii

Automation In The Design Of Asynchronous Sequential Circuits

Sequential switching circuits are commonly classified as being either synchronous or asynchronous. Clock pulses synchronize the operations of the synchronous circuit. The operation of an asynchronous circuit is usually assumed to be independent of such clocks. The operating speed of an asynchronous circuit is thus limited only by basic device speed. One disadvantage of asynchronous circuit design has been the complexity of the synthesis procedures for large circuits

Next-state equation generation for asynchronous sequential circuits - normal mode

This paper describes the known methods of generating next-state equations for asynchronous sequential circuits operating in normal fundamental mode. First, the methods that have been previously developed by other authors are explained and correlated in a simple and uniform language in order that the subtle differences of these approaches can be seen. This review is then followed by a development of a new method for generating minimal next-state equations which has some advantages over the previous methods. From the comparison of the previous known methods, it is noted that any one of these methods may be desirable for certain designs since each has some advantages that the others do not have. However, these methods also have limitations in that some methods can only be used with particular types of assignments. Also, as flow tables become larger the amount of work required to use some of these methods becomes excessive and tedious. The method developed here is a simple and straightforward approach which can be used for any unicode, single transition time assignment and will easily lend itself to computer application. The heart of this method emanates from the role that the Karnaugh map plays in the conventional approach for generating the next-state equations. The main advantage of this method seems to be its capability and proficiency in handling large flow tables --Abstract, pages ii-iii

Minimization and generation of next-state expressions for asynchronous sequential circuits

One step in the synthesis procedure for realizing an asynchronous sequential circuit that is operating in fundamental mode is to obtain an internal-state assignment that will realize the operations of the circuit. Often the procedures that are used in accomplishing the above task generate several satisfactory assignments. The first part of this paper presents a method that will enable one to predict which of the internal-state assignments will yield a simpler set of next-state expressions. A second topic treated in this paper is one of presenting a method to generate the next-state expressions for an asynchronous sequential circuit directly from the internal-state assignment. An algorithm is presented for generating the next-state expressions without construction of the transition table --Abstract, page ii