A 1.2 V 500 MHz 32-bit carry-lookahead adder

[[abstract]]In this paper a 1.2 V 32-bit carry lookahead adder is proposed for high speed, low voltage applications. The proposed new 32-bit adder uses Non-full Voltage Swing True-Single-Phase-Clocking Logic (NSTSPC) to implement the proposed carry lookahead adder. Because the internal node of NSTSPC was non-full swing, its operation speed would be higher than the conventional TSPC. Moreover, the supply voltage for the new adder is 1.2 V, thus the power dissipation would also be reduced. The 32-bit CLA adder using 0.35 μm 1P4M CMOS technology with 1.2 V power supply could be operated at a 500 MHz clock frequency.[[conferencetype]]國際[[conferencedate]]20010902~20010905[[booktype]]紙本[[conferencelocation]]Malt

ANALYZING THE PERFORMANCE OF CARRY TREE ADDERS BASED ON FPGA’S

In this paper carry tree adders are known to have the best performance in VLSI designs. However, this performance advantage does not translate directly into FPGA implementations due to constraints on logic block configurations and routing overhead. This paper investigates three types of carry-tree adders (the Kogge-Stone, sparse Kogge-Stone, and spanning tree adder) and compares them to the simple Ripple Carry Adder (RCA) and Carry Skip Adder (CSA). These designs of varied bit-widths were implemented on a Xilinx Spartan 3E FPGA and delay measurements were made with a high-performance logic analyzer. Due to the presence of a fast carry-chain, the RCA designs exhibit better delay performance up to 128 bits. The carry-tree adders are expected to have a speed advantage over the RCA as bit widths approach 256

Performance evaluation of FPGA implementations of high-speed addition algorithms

Driven by the excellent properties of FPGAs and the need for high-performance and flexible computing machines, interest in FPGA-based computing machines has increased dramatically. Fixed-point adders are essential building blocks of any computing systems. In this work, various high-speed addition algorithms are implemented in FPGAs devices, and their performance is evaluated with the objective of finding and developing the most appropriate addition algorithms for implementing in FPGAs, and laying the ground-work for evaluating and constructing FPGA-based computing machines. The results demonstrate that the performance of adders built with the FPGAs dedicated carry logic combined with some other addition algorithms will be greatly improved, especially for larger adders.published_or_final_versio

Article 09415

ABSTRACT INTRODUCTION Today's there square measure a growing range of moveable applications requiring small-area low-power highoutturn electronic equipment. Therefore, circuits with low power utilization grow to be the foremost vital candidates for style of microprocessors and system mechanism. The battery technology doesn't advance at constant rate because the electronics technology and there's a imperfect amount of power on the market for the mobile systems. The goal of extending the battery lifetime of moveable natural philosophy is to cut back the energy consumed per mathematical process, however low power consumption doesn't primarily imply low energy. To execute associate mathematical process, a circuit will acquire through low power by continuance at terribly low frequency however it's going to take a really lasting to complete the operation. Adder is a standout amongest the most fundamental segments of a CPU ( Central processing unit), Arithmetic logic unit (ALU), and coasting point unit and location era like store or memory access unit. Then again, expanding interest for versatile supplies Such as phones, personal digital assistant (PDA), and Notebook PC, emerge the need of utilizing zone and Power proficient VLSI circuits. Conventional adder is one in all the chief essential components of a processor that decides its out turn, and for address era just if there should be an occurrence of reserve or operation the complete adder execution would have an impact on the system as a whole. a spread of full adders. Abuse static or dynamic logic gates are accounted within the literature. In this paper, have a tendency to propose a logical methodology to style 10-transistor full adders and 28t full adders. Our new adders even have the limit misfortune issue; in any case, the adders square measure supportive in bigger circuits like multipliers regardless of the edge misfortune disadvantage. a substitution full adder known as static energy recovery full adder utilizes exclusively 10 transistors that has the most modest sum scope of transistors and has reduces the power dissipation, for every Power decline is one in all the first issues in today's VLSI style techniques as a consequence of a few reasons one is that the long battery in operation life interest of movable gadgets and second is owing to expanding scope of transistors on one chip brings about high power dissipation. The power consumption for CMOS circuits is described by the following equation: P avg = P dynamic + P short circuit + P leak Pavg =fclkCLαiV 2 dd + fclkI short V dd + I leak V dd Clearly see that the power depends on different parameters as well as on supply voltage (Vdd). Lowering Vdd would significantly reduce the power consumption of the circuit. This basic concept would be utilized to improve the power performance of the adder in this paper

Using Carry Increment Adders to Enhance Energy Savings with Spanning-Tree Adder Structures

Hybrid adders have provided innovation in the field of digital arithmetic. These designs take the best parts of multiple implementations and improve results in terms of area, delay, or power. This work implements a 64-bit hybrid adder using a spanning-tree structure with the carry increment algorithm. Synthesis results are obtained for 45nm technology and show promising data when compared with an existing hybrid design

A comparative analysis of parallel prefix adders in 32nm and 45nm static CMOS technology

textBinary adders form a major part in various arithmetic logical operation units including multipliers, dividers and digital signal processors. Parallel prefix adders represent a set of efficient structures for binary addition, greatly suited for VLSI implementation due to their regularity and speed. This report is focused on the comparative analysis of 5 major types of parallel prefix adder frameworks namely Kooge-Stone, Knowles adders, Brent-Kung, Han-Carlson and Ladner-Fischer adders implemented in Synopsys's SAED 32nm static CMOS technology operating at 1.05V for 8-bit, 16-bit and 32-bit input vectors based on power, performance and area (PPA) metrics. The process technology is modeled with 9 metal tracks. Power, performance and area metrics based on circuit simulations are used for comparison. The metrics are compared across SAED 32nm and FreePDK 45nm technology to quantify the impact of technology on architecture.Electrical and Computer Engineerin

Design and Implementation of Fault Tolerant Adders on Field Programmable Gate Arrays

Fault tolerance on various adder architectures implemented on Field Programmable Gate Arrays (FPGAs) is studied in this thesis. This involves developing error detection and correction techniques for the sparse Kogge-Stone adder and comparing it with Triple Modular Redundancy (TMR) techniques. Fault tolerance is implemented on a Kogge-Stone adder by taking advantage of the inherent redundancy in the carry tree. On a sparse Kogge-Stone adder, fault tolerance is realized by introducing additional ripple carry adders into the design. The implementation of this fault tolerance approach on the sparse Kogge-Stone adder is successfully completed and verified by introducing faults either on the ripple carry adder or in the carry tree. Two types of Xilinx FPGAs were used in this study: the Spartan 3E and Virtex 5. The fault tolerant adders were analyzed in terms of their delay and resource utilization as a function of the widths of the adders. The results of this research provide important design guidelines for the implementation of fault tolerant adders on FPGAs. The Triple Modular Redundancy-Ripple Carry Adder (TMR-RCA) is the most efficient approach for fault tolerant design on an FPGA in terms of its resources due to its simplicity and the ability to take advantage of the fast-carry chain. However, for very large bit widths, there are indications that the sparse Kogge-Stone adder offers superior performance over an RCA when implemented on an FPGA. Two fault tolerant approaches were implemented using a sparse Kogge-Stone architecture. First, a fault tolerant sparse Kogge-Stone adder is designed by taking advantage of the existing ripple carry adders in the architecture and adopting a similar approach to the TMR-RCA by inserting two additional ripple carry adders into the design. Second, a graceful degradation approach is implemented with the sparse Kogge-Stone adder. In this approach, a faulty block is permanently replaced with a spare block. As the spare block is initially used for fault checking, the fault tolerant capability of the circuit is degraded in order to continue fault-free operation. The adder delay is smaller for the graceful degradation approach by approximately 1 ns from measured results and 2 ns from the synthesis results independent of the bit widths when compared with the fault tolerant Kogge-Stone adder. However, the resource utilization is similar for both adders