A Low Temperature Co-fired Ceramic (LTCC) Interposer Based Three-Dimensional Stacked Wire Bondless Power Module

The objective of this dissertation research is to develop a low temperature co-fired ceramic (LTCC) interposer-based module-level 3-D wire bondless stacked power module. As part of the dissertation work, the 3-D wire bondless stack is designed, simulated, fabricated and characterized. The 3-D wire bondless stack is realized with two stand-alone power modules in a half-bridge configuration. Each stand-alone power module consists of two 1200 V 25 A silicon insulated-gate bipolar transistor (IGBT) devices in parallel and two 1200 V 20 A Schottky barrier diodes (SBD) in an antiparallel configuration. A novel interconnection scheme with conductive clamps and a spring loaded LTCC interposer is introduced to establish electrical connection between the stand-alone power modules to connect them in series to realize a half-bridge stack. Process development to fabricate the LTCC based 3-D stack is performed. In traditional power modules, wire bonds are used as a top side interconnections that introduce additional parasitic inductance in the current conduction path and prone to failure mechanism under high thermomechanical stresses. The loop inductance of the proposed 3-D half-bridge module exhibits 71% lower parasitic inductance compared to a wire bonded module. The 3-D stack exhibits better switching performance compared to the wire bonded counterpart. The measurement results for the 3-D stack shows 30% decrease in current overshoot at turn-on and 43% voltage overshoot at turn-off compared to the wire bonded module. Through measurements, it has been shown that the conducted noise reduces by 20 dB in the frequency range 20-30 MHz for the 3-D stack compared to the wire bonded counterpart. A simulation methodology using co-simulation techniques using ANSYS EM software tools is developed to predict EMI of a power module. Hardware verification of the proposed simulation methodology is performed to validate the co-simulation technique. The correlation coefficient between the measurement and simulation is found to be 0.73. It is shown that 53% of the variability in the simulation can be explained by the simulated result. Moreover, the simulated and measured amplitudes of the EMI spectrum closely match with each other with some variations due to round-off errors due to the FFT conversion

The Development of Novel Interconnection Technologies for 3D Packaging of Wire Bondless Silicon Carbide Power Modules

This dissertation advances the cause for the 3D packaging and integration of silicon carbide power modules. 3D wire bondless approaches adopted for enhancing the performance of silicon power modules were surveyed, and their merits were assessed to serve as a vision for the future of SiC power packaging. Current efforts pursuing 3D wire bondless SiC power modules were investigated, and the concept for a novel SiC power module was discussed. This highly-integrated SiC power module was assessed for feasibility, with a focus on achieving ultralow parasitic inductances in the critical switching loops. This will enable higher switching frequencies, leading to a reduction in the size of the passive devices in the system and resulting in systems with lower weight and volume. The proposed concept yielded an order-of-magnitude reduction in system parasitics, alongside the possibility of a compact system integration. The technological barriers to realizing these concepts were identified, and solutions for novel interconnection schemes were proposed and evaluated. A novel sintered silver preform was developed to facilitate flip-chip interconnections for a bare-die power device while operating in a high ambient temperature. The preform was demonstrated to have 3.75× more bonding strength than a conventional sintered silver bond and passed rigorous thermal shock tests. A chip-scale and flip-chip capable power device was also developed. The novel package combined the ease of assembly of a discrete device with a performance exceeding a wire bonded module. It occupied a 14× smaller footprint than a discrete device, and offered power loop inductances which were less than a third of a conventional wire bonded module. A detailed manufacturing process flow and qualification is included in this dissertation. These novel devices were implemented in various electrical systems—a discrete Schottky barrier diode package, a half-bridge module with external gate drive, and finally a half-bridge with integrated gate driver in-module. The results of these investigations have been reported and their benefits assessed. The wire bondless modules showed \u3c 5% overshoot under all test conditions. No observable detrimental effects due to dv/dt were observed for any of the modules even under aggressive voltage slew rates of 20-25 V/ns

Evaluation of SiC Schottky diodes using pressure contacts

The thermomechanical reliability of SiC power devices and modules is increasingly becoming of interest especially for high power applications where power cycling performance is critical. Press-pack assemblies are a trusted and reliable packaging solution that has traditionally been used for high power thyristor- based applications in FACTS/HVDC, although press-pack IGBTs have become commercially available more recently. These press-pack IGBTs require anti-parallel PiN diodes for enabling reverse conduction capability. In these high power applications, paralleling chips for high current conduction capability is a requirement, hence, electrothermal stability during current sharing is critical. SiC Schottky diodes not only exhibit the advantages of wide bandgap technology compared to silicon PiN diodes, but they have significantly lower zero temperature coefficient (ZTC) meaning they are more electrothermally stable. The lower ZTC is due to the unipolar nature of SiC Schottky diodes as opposed to the bipolar nature of PiN diodes. This paper investigates the implementation and reliability of SiC Schottky diodes in press-pack assemblies. The impact of pressure loss on the electrothermal stability of parallel devices is investigated

Towards a More Flexible, Sustainable, Efficient and Reliable Induction Cooking: A Power Semiconductor Device Perspective

Esta tesis tiene como objetivo fundamental la mejora de la flexibilidad, sostenibilidad, eficiencia y fiabilidad de las cocinas de inducción por medio de la utilización de dispositivos semiconductores de potencia: Dentro de este marco, existe una funcionalidad que presenta un amplio rango de mejora. Se trata de la función de multiplexación de potencia, la cual pretende resolverse de una manera más eficaz por medio de la sustitución de los comúnmente utilizados relés electromecánicos por dispositivos de estado sólido. De entre todas las posibles implementaciones, se ha identificado entre las más prometedoras a aquellas basadas en dispositivos de alta movilidad de electrones (HEMT) de Nitruro de Galio (GaN) y de aquellas basadas en Carburo de Silicio (SiC), pues presentan unas características muy superiores a los relés a los que se pretende sustituir. Por el contrario, otras soluciones que inicialmente parecían ser muy prometedoras, como los MOSFETs de Súper-Unión, han presentado una serie de comportamientos anómalos, que han sido estudiados minuciosamente por medio de simulaciones físicas a nivel de chip. Además, se analiza en distintas condiciones la capacidad en cortocircuito de dispositivos convencionalmente empleados en cocinas de inducción, como son los IGBTs, tratándose de encontrar el equilibrio entre un comportamiento robusto al tiempo que se mantienen bajas las pérdidas de potencia. Por otra parte, también se estudia la robustez y fiabilidad de varios GaN HEMT de 600- 650 V tanto de forma experimental como por medio de simulaciones físicas. Finalmente se aborda el cálculo de las pérdidas de potencia en convertidores de potencia resonantes empleando técnicas de termografía infrarroja. Por medio de esta técnica no solo es posible medir de forma precisa las diferentes contribuciones de las pérdidas, sino que también es posible apreciar cómo se distribuye la corriente a nivel de chip cuando, por ejemplo, el componente opera en modo de conmutación dura. Como resultado, se obtiene información relevante relacionada con modos de fallo. Además, también ha sido aprovechar las caracterizaciones realizadas para obtener un modelo térmico de simulación.This thesis is focused on addressing a more flexible, sustainable, efficient and reliable induction cooking approach from a power semiconductor device perspective. In this framework, this PhD Thesis has identified the following activities to cover such demands: In view of the growing interest for an effective power multiplexing in Induction Heating (IH) applications, improved and efficient Solid State Relays (SSRs) as an alternative to the electromechanical relays (EMRs) are deeply investigated. In this context, emerging Gallium Nitride (GaN) High‐Electron‐Mobility Transistors (GaN HEMTs) and Silicon Carbide (SiC) based devices are identified as potential candidates for the mentioned application, featuring several improved characteristics over EMRs. On the contrary, other solutions, which seemed to be very promising, resulted to suffer from anomalous behaviors; i.e. SJ MOSFETs are thoroughly analysed by electro‐thermal physical simulations at the device level. Additionally, the Short Circuit (SC) capability of power semiconductor devices employed or with potential to be used in IH appliances is also analysed. On the one hand, conventional IGBTs SC behavior is evaluated under different test conditions so that to obtain the trade‐off between ruggedness and low power losses. Moreover, ruggedness and reliability of several normally‐off 600‐650 V GaN HEMTs are deeply investigated by experimentation and physics‐based simulation. Finally, power losses calculation at die‐level is performed for resonant power converters by means of using Infrared Thermography (IRT). This method assists to determine, at the die‐level, the power losses and current distribution in IGBTs used in resonant soft‐switching power converters when functioning within or outside the Zero Voltage Switching (ZVS) condition. As a result, relevant information is obtained related to decreasing the power losses during commutation in the final application, and a thermal model is extracted for simulation purposes.<br /

A Double-Sided Stack Low-Inductance Wire-Bondless SiC Power Module with a Ceramic Interposer

The objective of this dissertation research is to develop a novel three-dimensional (3-D) wire bondless power module package for silicon carbide (SiC) power devices to achieve a low parasitic inductance and an improved thermal performance. A half-bridge module consisting of 900-V SiC MOSFETs is realized to minimize stray parasitic inductance as well as to provide both vertical and horizontal cooling paths to maximize heat dissipation. The proposed 3-D power module package was designed, simulated, fabricated and tested. In this module, low temperature co-fired ceramic (LTCC) substrate with vias is utilized as an interposer of which both top and bottom sides are used as die attachment surfaces, the SiC MOSFET bare dies are flip-chip attached on the LTCC interposer using nickel-plated copper balls, high horizontally thermal conductive material is integrated into the LTCC interposer to improve its thermal dissipation capability. Hence, the LTCC interposer provides both electrical and thermal routing and the nickel-plated copper balls replace bond wires in conventional planar power module as the electrical interconnections for the SiC power devices. On the other side, direct bond copper (DBC) substrate are used at both top and bottom sides of the 3-D module to achieve electrical path for SiC devices and double-sided cooling. As a result, 3D power routing is achieved to reduce stray inductance, and both vertical and lateral paths are utilized to spread heat generated by the power devices in this compact module architecture. Electrical simulation was performed to extract the parasitic inductances in the 3-D package and compared to other reported module packages. Low loop parasitic inductance of 4.5nH at a frequency of 1MHz is achieved after optimization. Thermal and thermo-mechanical simulations were also conducted to evaluate the thermal performance and mechanical stress of the proposed module structure. The fabrication process flow of the 3-D wire bondless module is developed and presented. The fabricated half-bridge module was evaluated experimentally by double-pulse test and thermal cycling test. Significant reduction in voltage overshoot and ringing was observed during the double-pulse test, and the module shows no degradation after thermal cycling test. To push the double-sided wire-bondless module to higher voltage application, a 3.3-kV SiC double-sided wire-bondless common source module was designed, fabricated, and tested. Electric field simulations were performed considering the associated challenge of increased electric field strength in the higher-voltage wire-bondless module. High voltage blocking test was added to evaluate the high voltage operation capability as well